The quest for a simple FST4W tx - WARNING !!!
As part of confirming everything prior to sending off Reference
boards for QDX systems I've discovered a serious problem.
In a nutshell I think it is possible to blow out the QDX finals if external clocking isn't done carefully. At this point I think it is actually a QDX design problem.
As part of getting some GPS and Reference boards ready to send
out I thought I should actually drive the QDX with a configured
Reference - I've actully been using a Bodnar Mini. On my QDX
Ihave C54 lifted and a cable run to the back panel for the
external clock injection I've been using. Both the Bodnar Mini
which I've been using and the Reference have very similar output
levels, as you'd expect, they both come from Si5351's. There is a
slight difference though, the Bodnar Mini has no DC blocking
capacitor so the ~ +12 dBm that comes out has a DC offset on it
while I put a blocking capacitor into my Reference.
In the process of moving the sourcing of the 25 MHz clock, I
evidently did it live, with power on the QDX which during the
cable swapping at least means no external clock signal comes in
for a short while. As we know this stops the QDX and requires
complete restart since USB comms and everything goes away. I knew
to restart everything. What I didn't expect is to see a
significant difference after a source was returned. What I found
was that not only did the two sources work differently but I had
lost transmit power, output down to -45 dBm or something. I think
I've blown out at least half of the QDX output devices. That is
leading me to ask "Why?". The clock buffer looks like:
and the PA looks like
Since I had already used C54 to DC block and couple signal from the Bodnar and already had the QDX connected via DC blocking capacitor, what could possibly be wrong?
I can now think of something. In the absence of clock on the
SI5351 It's clock outputs are in a still-unknown-to-me state.
I note that very bad things happen when both CK0 and CK1 are stuck at the wrong logic levels of 'on' for both pull up and pull-down enhancement FETs. The outputs then fight each other and some or all will no doubt lose that battle. So much for the blown PA(s) I expect to find.
But there may be more, why the difference in sources of
same-amplitude signals one with a DC term and one already DC
blocked? Possibly the charging current for C54 serves to force
the output of the Clock buffer to a level that did NOT leave the
PA FETs fighting? Or possibly I just got un-lucky and a QDX with
no-clock at power-on can have this problem one out of four times,
when the Si5351 happens to get power and leave its clk1 and clk2
lines in exactly the wrong condition. I don't know yet but hope to
More to study but meanwhile I'm off of 20m FST4W and I recommend
that anyne externally clocking a QDX be very careful to have a
clock present whenever the QDX starts and always during operation.
Even a bad cable might blow out your PAs!
On 13/01/2023 17:53, Glenn Elmore wrote:
I think it is possible to blow out the QDX finals if external clocking isn't done carefully. At this point I think it is actually a QDX design problem.Glen,
Possibly, the QDX has gone through quite a few firmware updates and has still a few things outstanding.
PA failure has been reported, sometimes it appears no explanation, sometimes explained as the result of bad loading.
I do not expect that any guard against a lack of clocking has been made although the PA should not be activated until TX is initiated.
Like most QRP Labs projects it is a minimalist design.
73 Alan G4ZFQ
Thanks Alan, I had wondered if mysterious PA failures might have been noted, either at first power after assembly or other times but hadn't searched the forums. Operation under unspecified conditions, loss of one power supply in the presence of another and other atypical situations can be a headache and hard to even think of. I don't fault Hans too much for missing this one, if in fact he has.toggle quoted message Show quoted text
I'm hoping it doesn't really need parallel gates (interesting!) to get enough drive current or short enough rise time to keep efficiency suitably high. If he doesn't, it may be that a logical lock out making it impossible to reach the 'all PAs on' condition even when the Si5351 is sending clocks that request that with no additional components on the PCB may be possible.
If/when I know a little more about the failure mode I may write to him. The QDX is such a good fit for FST4W on HF and the resulting spots and ionospheric studies that I'd really like it all to work.
On 1/13/23 12:01, Alan G4ZFQ wrote:
Well, False Alarm, (I think), more like an (im)perfect storm
After looking to understand the QDX failure, I discovered that there "pretty much wasn't one." Rather my 30 dB HP power attenuator, a fixed 30 dB pad and a calibration check connection all failed at the same time to similar high loss values and for an as yet unknown reason I couldn't hear the QDX through the remote 20 km distant.
When I took the QDX apart I did find a failed FET, but only one. That FET had lost all G but its mate was working. I replaced all four and proceeded to measure. At which point the spectrum analyzer with either the power attenuator of 2 N attenuators both agreed that power was very low. I looked at levels and switched LPFs with the VNA and everything was fine. The scope said not only were there lots of p-p volts on the FET drains but also at both the input and output of the LPF. Then comparing the scope on the same BNC tee as the SA I still found disagreement.
I checked SA calibration (changed connections) with the same pad and it was OK. Huh? Same line nut scope and SA were ten's of dB different. I won't go through it all but:
In email discussion with Hans he feels confident that the Si5351 clock lines can not leave a line stuck high under loss of input clock or other mechanisms which would destroy the FETs, even loss of CPU clock which programs the Si5351. Maybe we need not worry as much about assuring presence of external QDX clock before and during power application.
My current status is,
But more importantly, maybe QDXs with external 25 MHz clocking are still good candidates for FST4W. Let's hope so.
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