Hello,

I would like to share my project about Odyssey 2 hopping that can be
useful to someone else.
I wrote from scratch a new programmer, a new MCU firmware, and made
changes to the Bootloader and to Radio firmware.

The main changes that I made to the respect of N7DDC are the following:

- fully remote configuration of the bootloader (also remote entering);
not MIC needed;
- the new MCU firmware uses free Microchip XC8 compiler and source code
is provided;
- the programmer is a terminal program (for now) and it is written in
C89 to be future proof and be available on any platform; basic commands
work with N7DDC bootloader (like slot programming) but it implements
many others to control the configuration and the
bootloader;
- more agile protocol between MCU and FPGA;
- each radio stage is shown on the display;
- comments everywhere;
- comprehensive documentation.

You can find the resository at
https://github.com/ra1nb0w/odyssey2sdr

In the releases page you can find all binaries.

Each sub-section page like programmer, mcu and radio contains a Readme
that describe the functionalities and the protocol.

Now I am working on:

- updating the radio firmware to Angelia V12 (not easy since there are not changeset)
- calculating the SWR on FPGA (MCU part is already done)

Feel free to send me your suggestions, open an issue or a pull request.

Have a nice week
/davide

On Tuesday, 21/07/2020 01:28 CEST, Robson Pereira <robson.apereira@gmail.com> wrote:

Thanks for putting together this excellent GIT repository. Quite amazing!!

This will be a great reference when building and testing this project.

thank you sir.

Have you considered documenting the schematics if there is a way to create
the schematics from a PCB?

No. Some parts are the same of Angelia/Anan100D board [1] (like RX) the
others can be quite easily followed with the Spring Layout software.
Maybe Altium can create schematics from a netlists (probably with a very
bad placement) but the effort seems useless to me since you can navigate the
layout. If you do it feel free to open a pull request.

/davide

[1] https://github.com/ra1nb0w/odyssey2sdr/blob/master/pcb/schematics/Angelia-Anan100D.pdf

Hi Davide, 

Hello Davide, 

Thanks for making your project availlable to the community!!

I have a question for the mcu compilation. You wrote: 

Reto, good question !
I would like to know how a firmware determines different  voltage of logic 1 on the same output port .
Very interesting.

On Thursday, 23/07/2020 01:41 CEST, Reto HB9TRT <hb9trt@gmail.com> wrote:

Hello Davide,

** Notes

- when you flash this firmware over N7DDC you need to re-calibrate the
PD85004s resistor since the RA2 voltage is different.

I don't understand what I have to change or recalibrate. Could you
explain what you mean with re-calibrate the PD85004 resistor?

With re-calibrate I mean changing the 10K trimmer value placed near the
two PD85004s. This is necessary, to answer David's question, because
I am not using RA2 as digital output but as DACOUT with fixed voltage
reference (FVR) as back-end (4.096V). Since this is a lower value you
need to change a bit the resistor's value to obtain the same output.

The PIC code can be grasped at
https://github.com/ra1nb0w/odyssey2sdr/blob/master/mcu/16F1827.c#L62

Note from datasheet:

IF DACEN = 0 and DACLPS = 1 and DACR[4:0] = 11111
VOUT = VSOURCE

VSOURCE is FVR in my case.

On Thursday, 23/07/2020 08:00 CEST, Davide Gerhard via groups.io <rainbow=irh.it@groups.io> wrote:

I am not using RA2 as digital output but as DACOUT with fixed voltage
reference (FVR) as back-end (4.096V). Since this is a lower value you
need to change a bit the resistor's value to obtain the same output.

Ps. I am not sure that using FVR is fine in every situation so
suggestions/comments are welcome :)

Hello, Davide.
I am not sure, but I think for some pd85004 4 Volts would be not enough to reach 125mA current. They are have very different required bias voltage.

Hi Davide and David, 

I think now I understand what you mean. I'm readeing what you both discussed. Very interesting. I'll try it out if I'm able to compile the MCU firmware and get a .hex. Until now I have no success. The FPGA Bootloader and Radio firmware I compiled successfully with quartus (I took 18.1) and I saw, that the .rbf was generated at the same time as the .pof file. 
With your mcu file and bootloader is it possible to load David's ANP and AOP firmares in other slots too? work they with your bootloader?

vy 73
Reto

On Friday, 24/07/2020 00:05 CEST, Reto HB9TRT <hb9trt@gmail.com> wrote:

Hi Davide and David,

Bootloader and Radio firmware I compiled successfully with quartus (I
took 18.1) and I saw, that the .rbf was generated at the same time as
the .pof file.

you can find all binaries at
https://github.com/ra1nb0w/odyssey2sdr/releases/tag/3.0

what is your problem building the MCU?
Probably you need to open the project with MPLAB IDE and reconfigure the
compiler folder. At first opportunity, I will remove that part and use
plain make file and should work easily with any platform.

With your mcu file and bootloader is it possible to load David's ANP
and AOP firmares in other slots too? work they with your bootloader?

No, we are using different channel between MCU and FPGA.
Anyway, they are the same code and the only change for the moment is
that channel. The basic functionalities of the programmer can be used
with David's Bootloader; essentially, the same functions that are
present in his programmer.

Hi Davide 

Thanks for your reply. I try with your compiled files first. I tried yesterday and got a non-working mcu binary. I have to test first. I never worked with pic before, only with atmega. So the environnement is new for me. I tested a little bit with fpga and quartus. I have a little test board with a max II and so a easy way to work in the complex world of the fpga. 

Now I'll try with your binaries. 

Vy 73 
Reto 

On Thursday, 23/07/2020 16:23 CEST, David Fainitski <rolin791@gmail.com> wrote:

Hello, Davide.
I am not sure, but I think for some pd85004 4 Volts would be not
enough to reach 125mA current. They are have very different required
bias voltage.

Since I am not a power amplifier expert and therefore I can't see all
practical implications I wrote my statements to a friend that works at
ST RF department; he confirmed those statements hence I report here what
I wrote.

I have the attached circuit as power amplifier on my radio where
Vd = 12V and I need to reach Id = 100mA in quiescent mode using Vgs
between 3 to 4 Volts to use the fixed voltage reference of PIC. The
datasheet states that Vgs can be from -0.5 to +15 Volts and Figure 3 and
4 should confirm that the LdmoSTs should work fine on that range of gate
voltage. I did a few tests measuring current consumption in quiescent
mode and in ON mode (with three duty cycles) and Vgs between 3 to 4
volts fulfill the required stability and current. I also found confirm
on this from others ham that are using 3.3V as gate voltage (EMRFD
discussion group).

Said that, I would like to use that fixed voltage reference of the PIC
because MOS has quite big transconductance and therefore they are
sensible on the input voltage. The PIC datasheet doesn't state
explicitly (or I don't found) that RA2 port is temperature
controlled but the temperature module is integrated on the fixed voltage
indicator. We also need to take in consideration that we can have a NTC
component.

Hello Davide, 

The link to the binaries does not work anymore. I tried it before. 
It seems the directory was deleted. 

vy 73
Reto

Hello Davide and Peter 

I found the binaries with David's link. Now it's installed and I can try. Loading firmware worked well. Also enter borloder with option -b

At the test I got sometimes FPGA Error. After reboot it works. 

TX I don't test until now. I'll see if I can adjust the correct bias. 

What do you change in the firmware files? I mean what are the difference from the original ones? I not talk about mcu and bootloader. This is documented. But the firmware files which will be programmed with the Exe file over network interface. 

Vy73
Reto 

Reto HB9TRT <hb9trt@gmail.com> writes:

What do you change in the firmware files? I mean what are the difference from the original ones? I not talk about mcu and bootloader. This is documented. But the firmware files which will be programmed with the Exe file over network interface.

FPGA gateware: that release is pretty similar to N7DCC excepts the
protocol communication with MCU and comments.
The master branch contains the protocol 1 aligned with TAPR version and
it works fine.
In the angelia2 branch there is an under-testing protocol 2 gateware
that is aligned with TAPR version (therefore all fixes released for the
Anan 100D) with a macro to choose which Ext.IO type to use (N7DDC custom
or openHPSDR/Alex version) and minor changes.

Hi Davide, 

Thanks for explaining the changes in the two firmware files. Until now it works fine so far. 

Today I tried something on the raspberry and I tried to compile the programmer. But no success. gcc and mak is installed. I'm sure I make something wrong. 

If I execute "make" I got several errors: 

 

cc -std=c89 -o programmer main.c

main.c:67:20: error: ‘PATH_MAX’ undeclared here (not in a function); did you mean ‘AF_MAX’?

 char firmware_file[PATH_MAX+1];

                    ^~~~~~~~

                    AF_MAX

main.c: In function ‘set_timeout’:

main.c:284:18: error: storage size of ‘timeout’ isn’t known

   struct timeval timeout;

                  ^~~~~~~

main.c: In function ‘change_ip’:

main.c:525:22: warning: initialization of ‘char *’ from ‘int’ makes pointer from integer without a cast [-Wint-conversion]

   char *new_ip_tmp = strdup(odyssey2.new_ip);

                      ^~~~~~

make: *** [Makefile:8: programmer] Fehler 1

Reto HB9TRT <hb9trt@gmail.com> writes:

Hi Davide,

Today I tried something on the raspberry and I tried to compile the programmer. But no success. gcc and mak is installed. I'm sure I make something wrong.

I fixed the Linux build after that release therefore if you need to
build it you need to download the master code [1]. Sorry for the
confusion; I expected to conclude the TAPR alignment this August and
to release a new version but I did other things.

[1] https://github.com/ra1nb0w/odyssey2sdr/archive/master.zip