Topics

building Ody2

Marc olanie
 

Hi
I'd like to know
- which device should be soldered on the bottom side, between the TX out and the VNA in ? (the footprint is labeled "340" and is rather large)
- what is the value of the components located on the lower side (I imagine 100nF decoupling caps, 0603, 10 o 16V rated, but a confirmation would be perfect) 

FYI, the footprint of the "phone" jack has been modified. The front plastic centering pin cannot "sit" in its place and shoud be cut. Not very important, but should be corrected if a new run of pcb should be ordered. 
734
Marc





Marc olanie
 

To myself and I

"read the f... manual, you bonehead !" (it's a 340 Ohms 1W resistor, David specified it in the instruction list)

... and I used 100nF decoupling caps for the fpga, I doubt it will hurt anything :- D 

73'
Marc f6itu

dan edwards
 

on dit 'RTFM' n'est-ce pas??

ha ha 73, w5xz, dan


On Monday, September 16, 2019, 03:42:32 PM CDT, Marc olanie <Marc.olanie@...> wrote:


To myself and I

"read the f... manual, you bonehead !" (it's a 340 Ohms 1W resistor, David specified it in the instruction list)

... and I used 100nF decoupling caps for the fpga, I doubt it will hurt anything :- D 

73'
Marc f6itu

Marc olanie
 

>on dit 'RTFM' n'est-ce pas??

 

Definitely. Even in French :- ) If I received a quarter each time I had to repeat this mantra, I would be rich… incredibly rich

 

But, in my defence,  looking for  the value of a resistor (or discovering the fact that a resistor should be placed here) is generaly done by a schematic, not a manual :- o

 

Still some components to find (and a 1W resistor among them), and I will bug the list with more than stupid questions about the bootloader, firmware and gateware things.

 

73 to all

Marc f6itu

Marc olanie
 

Yet  another building question : 
where is located the 100k NTC ? 

Looking for it for more than 2 hours...  in vain
73'
Marc f6itu

Leo Goto
 

Hi Marc f6itu,

I think *T.
But I am not sure.
I attached photo.

Leo,


On Mon, 16 Sep 2019 23:52:08 -0700
"Marc olanie" <Marc.olanie@...> wrote:

Marc f6itu
--
Leo Gotoh <LeoGoto@...>
http://travelx.org

Marc olanie
 

Thanks Leo
That's what I though at first glance  (logically in the bias circuit, close to the RF Push-pull) 
I'll wait for a final confirmation from David
Tnks agn
Marc f6itu

David Fainitski
 

Hi
Yes,  that is right. Leo is odyssey's expert now. 

Marc olanie
 

Hi
While waiting for the last caps and my main oscillator... two other questions.

- On the "Ext. I/O" connector, SPI outputs, which "enable"  output has been chosen in the gateware ? TX or RX ? 
In other words, which part of the Alex protocol has been kept intact ? LPF and the 3 TX output, or HPF and the Xvtr/RX2/RX3/Bypass & external attenuator ? 
 
-  refl and fwd pwr on adc1 & adc2, I imagine, should be used in the same conditions needed by the hpsdr gateware (0/3.3v max for each input, control via PowerSDR.kisskonsole etc) 

This question just to know which filter I'll use, with which config and how I'll be able to control them
73'
Marc f6itu

Marc olanie
 

Thanks for the confirmation David. More questions to come :- ) 

Marc

David Fainitski
 

- On the "Ext. I/O" connector, SPI outputs, which "enable"  output has been chosen in the gateware ? TX or RX ? 
In other words, which part of the Alex protocol has been kept intact ? LPF and the 3 TX output, or HPF and the Xvtr/RX2/RX3/Bypass & external attenuator ?

If you want to use SPI control, here is the schematic of decoder

http://ody-sdr.com/wp-content/uploads/2017/09/SPI_decoder.jpg
Description of outputs here ( from SPI.v, firmware sources):

*****************************************

Modified by David Fainitski

for Odyssey-2 TRX project

2017

Bit       Function           I.C. Output

------ ------------             -----------

Bit 00 - 160 Meters LPF U1 - D0

Bit 01 - 80 Meters  LPF U1 - D1

Bit 02 - 60/40 Meters LPF U1 - D2

Bit 03 - 30/20 Meters LPF U1 - D3

Bit 04 - 17/15 Meters LPF  U1 - D4

Bit 05 - 12/10 Meters         U1 - D5

Bit 06 - 1.5 MHz HPF        U1 - D6

Bit 07 - 6.5 MHz HPF U1 - D7

Bit 08 - 9.5 MHz HPF    U2 - D0

Bit 09 - 13 MHz HPF         U2 - D1

Bit 10 - 20 MHz HPF        U2 - D2

Bit 11 - Bypass                U2 - D3

Bit 12 - 6M Preamp          U2 - D4

Bit 13 - ANT #2                  U2 - D5

Bit 14 - ANT #3                 U2 - D6

 

Bit 15 - Tx/Rx Relay           U2 - D7

This will work like Alex board control with the same cons. and pros.

Other way, you can use 7 User Outputs + ANT control pin and use filters which you want with no restrictions. Just install demultiplexer and have up to 127 control lines



On this screenshot, only 3 User Outputs and 7 control lines after demultiplexer enough for me for control my own LPF HPF

See the schematic https://easyeda.com/rolin791/HFPU-100

 

Marc olanie
 

Thanks a lot, David

In fact, that was not exactly the question. I was wondering which "branch" of the spi bus you chose, as the Alex protocol needs 2 Enable lines to be fully functional, and not only one. With only one, I'll have to butcher the cabling of my Alex frontend to fit the ody reassignment. 

This is not important anymore. I stoped working on this project, as the fpga 1.2V rail has a short to ground, and Sprint Layout is hardly able to give me the full equipotential. Without schematic, it would be quite impossible to find such a bug, and I don't imagine spending more money, buying a new board and a new fpga. 

Anyhow, a big thanks you to you, David. For your efforts, for your involvment in this project, and for your ideas. 
Wish you a nice week-end
Marc


David Fainitski
 

Hello,  Mark
1.2V bus shorting is a simple thing in the assembly process.  You don't need the schematic to find shortened blocking capacitor on the bottom or shortened FPGA balls.  Also checking the FPGA key is aligned properly to board's key.