Thanks a lot, David
In fact, that was not exactly the question. I was wondering which "branch" of the spi bus you chose, as the Alex protocol needs 2 Enable lines to be fully functional, and not only one. With only one, I'll have to butcher the cabling of my Alex frontend to fit the ody reassignment.
This is not important anymore. I stoped working on this project, as the fpga 1.2V rail has a short to ground, and Sprint Layout is hardly able to give me the full equipotential. Without schematic, it would be quite impossible to find such a bug, and I don't imagine spending more money, buying a new board and a new fpga.
Anyhow, a big thanks you to you, David. For your efforts, for your involvment in this project, and for your ideas.
Wish you a nice week-end