Re: Transistor S parameter measurements

Peter Ide-Kostic <on7yi.pik973@...>


I only have experience measuring S parameters of LDMOS devices in the 1-500
Mhz range;

What is critical is to feed the transistor with a DC good choke system
(drain) and a good Bias system (Gate) which performs well in the frequency
range that you are measuring. Establishing that the DC Choke and bias
system perform well in the frequency range of interest is therefore an
extremely important pre-requisiste before doing any measurements. For
instance there is no point trying to measure an LDMOS in the 800-900 Mhz
range if the types of Chokes used on the drain stop being effective above
300 Mhz due to stray capacitance of the Choke.

Then there is the stability issue. Some transistors, especially old
generation ones with a relatively high drain-gate capacitor of 10-20 pf
(ie, miller capacitor) will tend to oscillate more easily spontaneously
(often resonating with the DC choke if is too high Q) than the modern ones
where the drain-gate capacitor is reduced to 1 or 2 pf only. Practically
this means that to be measurable, the transistor may need to be stabilized
with a combination of the following (a) shunt resistor between gate and
ground (b) serial resistor between gate and the source generator (c)
feedback resistor between gate and drain. Of course these stabilisation
resistors, when present, affect the measurement of the S
what is measured is not the parameter of the transistor but of the fixture
plus transistor. . Ideally it should be possible to deembed the effect of
those stabilizing resistors but I have not found any tools that allow to do
that easily. So, what I do instead , when a transistor requires to be
stabilised to be measured, is to make a range of measurements with
different combination of stabilizing resistors (so I get a complete


On Wed, Sep 23, 2020 at 10:36 AM alan victor <avictor73@...> wrote:

On Tue, Sep 22, 2020 at 01:23 PM, Reginald Beardsley wrote:

I found some discussion over a year ago, but nothing since. Has anyone

I had trouble finding any information on fixture design. Ultimately I
on biasing the candidate transistor with PCB edge SMA-F connectors on a
and then with the appropriate appendages measuring it with the nanoVNA
possibly some other VNAs.

I just made up a bunch of bare fixture boards. First up is a 2N3904 in
form and no feedback. After that I thought I'd try CB and CC before
moving on
to feedback.

I know I'm not the only one interested, but I can't seem to find much
of prior work.

Have Fun!
I just made up a bunch of bare fixture boards. First up is a 2N3904 in CE
form and no feedback. After that I thought I'd try CB and CC before
moving on
to feedback.

One issue is the power level provided by the vna. At -12 dBm, unless
padded, this is quite a large signal. The newer vna units I believe have
the ability to adjust Pin lower. If the device is biased at low current,
say 1 mA, then the thermal voltage is ~ 26 mV. You really need to keep Pin
less than 1/10th of Vt or 2 mV and hence Pin of -30 dBm would be nice. At
HF a typical BIP has an S21 of 40 dB. CH1 will overload. So now padding CH1
is required. However, S12 is lower than -40 dB so now we have a dynamic
range issue. Getting s11 and s22 is not bad, since they are -10 and -3 dB

So, how did you handle the CH0 power issue? Did you use pads, cal and then
remove pads to finish up?

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