z/Architecture?


Jesus Antonio
 

Hi.


As I'm writing this I'm compiling the latest version of clang in hopes of circumventing the z/Architecture negative indexes code generation "bug" present on the GCC compiler. I also want to avoid the EBCDIC formatting problems present on GCC. Hopefully i can use EBCDIC normally without any barriers (such as spurious warnings).


Now for the main question: z/Architecture Hypervisor and Virtualization Technologies

I have recently taken interest in going further to develop UDOS into a more wide scope. This is by allowing UDOS to act as a hypervisor for let's say running z/OS under a VM and z/Linux too.

How can i accomplish this task, what hypervisor functionality i need? Is this even achievable?


Another question: Modifying IBM millicode

Achievable or outright impossible? I've heard it's not possible but i may be wrong.


How to drive the timer?

I'm trying to activate the timer, I'm using the SET TIMER and STORE timer instructions and set it to a positive value that should generate an external interrupt once it goes to the negative. But no external interruption is recognized - what am i doing wrong?


Adios.

- jesus


Joe Monk
 

"I have recently taken interest in going further to develop UDOS into a 
more wide scope. This is by allowing UDOS to act as a hypervisor for 
let's say running z/OS under a VM and z/Linux too."

The SIE instruction is IBM patented and licensed technology. Good luck with finding information on its operation and details.

"Another question: Modifying IBM millicode

Achievable or outright impossible? I've heard it's not possible but i 
may be wrong."

Not possible without physical access to the Hardware Support Element (a pair of 1U servers that are physically located inside the machine).

"How to drive the timer?

I'm trying to activate the timer, I'm using the SET TIMER and STORE 
timer instructions and set it to a positive value that should generate 
an external interrupt once it goes to the negative. But no external 
interruption is recognized - what am i doing wrong?"

Do you have interrupts enabled for the CPU timer? Bit 53 of control register 0 must be 1.

Joe

On Sat, Oct 23, 2021 at 12:37 PM Jesus Antonio <jesusantonio30122016@...> wrote:
Hi.


As I'm writing this I'm compiling the latest version of clang in hopes
of circumventing the z/Architecture negative indexes code generation
"bug" present on the GCC compiler. I also want to avoid the EBCDIC
formatting problems present on GCC. Hopefully i can use EBCDIC normally
without any barriers (such as spurious warnings).


Now for the main question: z/Architecture Hypervisor and Virtualization
Technologies

I have recently taken interest in going further to develop UDOS into a
more wide scope. This is by allowing UDOS to act as a hypervisor for
let's say running z/OS under a VM and z/Linux too.

How can i accomplish this task, what hypervisor functionality i need? Is
this even achievable?


Another question: Modifying IBM millicode

Achievable or outright impossible? I've heard it's not possible but i
may be wrong.


How to drive the timer?

I'm trying to activate the timer, I'm using the SET TIMER and STORE
timer instructions and set it to a positive value that should generate
an external interrupt once it goes to the negative. But no external
interruption is recognized - what am i doing wrong?


Adios.

- jesus







Jesus Antonio
 

Hi.


"The SIE instruction is IBM patented and licensed technology. Good luck with finding information on its operation and details."

Does it mean that I'm not able to utilize such technology without paying royalties/getting a license?


"Do you have interrupts enabled for the CPU timer? Bit 53 of control register 0 must be 1."

Yes, I made the PSW be set to allow CPU timers and i set the appropriate bits on CR0 as well.


I'm using ESA/390 by the way - However as i mentioned before the negative indices problem does not allow me to code for z/Architecture correctly.


Adios.

-jesus

On 23/10/21 13:36, Joe Monk wrote:
"I have recently taken interest in going further to develop UDOS into a 
more wide scope. This is by allowing UDOS to act as a hypervisor for 
let's say running z/OS under a VM and z/Linux too."

The SIE instruction is IBM patented and licensed technology. Good luck with finding information on its operation and details.

"Another question: Modifying IBM millicode

Achievable or outright impossible? I've heard it's not possible but i 
may be wrong."

Not possible without physical access to the Hardware Support Element (a pair of 1U servers that are physically located inside the machine).

"How to drive the timer?

I'm trying to activate the timer, I'm using the SET TIMER and STORE 
timer instructions and set it to a positive value that should generate 
an external interrupt once it goes to the negative. But no external 
interruption is recognized - what am i doing wrong?"

Do you have interrupts enabled for the CPU timer? Bit 53 of control register 0 must be 1.

Joe

On Sat, Oct 23, 2021 at 12:37 PM Jesus Antonio <jesusantonio30122016@...> wrote:
Hi.


As I'm writing this I'm compiling the latest version of clang in hopes
of circumventing the z/Architecture negative indexes code generation
"bug" present on the GCC compiler. I also want to avoid the EBCDIC
formatting problems present on GCC. Hopefully i can use EBCDIC normally
without any barriers (such as spurious warnings).


Now for the main question: z/Architecture Hypervisor and Virtualization
Technologies

I have recently taken interest in going further to develop UDOS into a
more wide scope. This is by allowing UDOS to act as a hypervisor for
let's say running z/OS under a VM and z/Linux too.

How can i accomplish this task, what hypervisor functionality i need? Is
this even achievable?


Another question: Modifying IBM millicode

Achievable or outright impossible? I've heard it's not possible but i
may be wrong.


How to drive the timer?

I'm trying to activate the timer, I'm using the SET TIMER and STORE
timer instructions and set it to a positive value that should generate
an external interrupt once it goes to the negative. But no external
interruption is recognized - what am i doing wrong?


Adios.

- jesus







Paul Edwards
 

On Sun, Oct 24, 2021 at 06:26 AM, Jesus Antonio wrote:

"The SIE instruction is IBM patented and licensed technology. Good luck
with finding information on its operation and details."

Does it mean that I'm not able to utilize such technology without paying
royalties/getting a license?
Patents only last 20 years. So long as you aren't using any
functionality that didn't exist in the first version of z/Arch,
you can do whatever you want.

I'm using ESA/390 by the way - However as i mentioned before the
negative indices problem does not allow me to code for z/Architecture
correctly.
Even with the negative indexes problem, there is no need
to use ESA/390. You can simply use AM31 in z/Arch instead
(ie don't BSM to AM64).

But if clang doesn't fix the problem for you, you might like to
try seeing if you can activate z/Arch DAT and get the 4 GiB
to 8 GiB virtual address space mapped on to 0 - 4 GiB real
memory. If you can get that to work you get the entire 4 GiB
region, even with negative indexes.

BFN. Paul.


Joe Monk
 

"Does it mean that I'm not able to utilize such technology without paying royalties/getting a license?"

Depends on how badly you infringe the patent! :)


Joe


On Sat, Oct 23, 2021 at 2:26 PM Jesus Antonio <jesusantonio30122016@...> wrote:

Hi.


"The SIE instruction is IBM patented and licensed technology. Good luck with finding information on its operation and details."

Does it mean that I'm not able to utilize such technology without paying royalties/getting a license?


"Do you have interrupts enabled for the CPU timer? Bit 53 of control register 0 must be 1."

Yes, I made the PSW be set to allow CPU timers and i set the appropriate bits on CR0 as well.


I'm using ESA/390 by the way - However as i mentioned before the negative indices problem does not allow me to code for z/Architecture correctly.


Adios.

-jesus

On 23/10/21 13:36, Joe Monk wrote:
"I have recently taken interest in going further to develop UDOS into a 
more wide scope. This is by allowing UDOS to act as a hypervisor for 
let's say running z/OS under a VM and z/Linux too."

The SIE instruction is IBM patented and licensed technology. Good luck with finding information on its operation and details.

"Another question: Modifying IBM millicode

Achievable or outright impossible? I've heard it's not possible but i 
may be wrong."

Not possible without physical access to the Hardware Support Element (a pair of 1U servers that are physically located inside the machine).

"How to drive the timer?

I'm trying to activate the timer, I'm using the SET TIMER and STORE 
timer instructions and set it to a positive value that should generate 
an external interrupt once it goes to the negative. But no external 
interruption is recognized - what am i doing wrong?"

Do you have interrupts enabled for the CPU timer? Bit 53 of control register 0 must be 1.

Joe

On Sat, Oct 23, 2021 at 12:37 PM Jesus Antonio <jesusantonio30122016@...> wrote:
Hi.


As I'm writing this I'm compiling the latest version of clang in hopes
of circumventing the z/Architecture negative indexes code generation
"bug" present on the GCC compiler. I also want to avoid the EBCDIC
formatting problems present on GCC. Hopefully i can use EBCDIC normally
without any barriers (such as spurious warnings).


Now for the main question: z/Architecture Hypervisor and Virtualization
Technologies

I have recently taken interest in going further to develop UDOS into a
more wide scope. This is by allowing UDOS to act as a hypervisor for
let's say running z/OS under a VM and z/Linux too.

How can i accomplish this task, what hypervisor functionality i need? Is
this even achievable?


Another question: Modifying IBM millicode

Achievable or outright impossible? I've heard it's not possible but i
may be wrong.


How to drive the timer?

I'm trying to activate the timer, I'm using the SET TIMER and STORE
timer instructions and set it to a positive value that should generate
an external interrupt once it goes to the negative. But no external
interruption is recognized - what am i doing wrong?


Adios.

- jesus







Joe Monk
 

"Patents only last 20 years. So long as you aren't using any
functionality that didn't exist in the first version of z/Arch,
you can do whatever you want."

Every time they come out with a new model of z/box, its a new patent iteration.

"get the 4 GiB
to 8 GiB virtual address space mapped on to 0 - 4 GiB real
memory."

DAT doesnt work that way.

z/Arch memory in DAT is broken into 3 parts: a region (2GB), a segment (1MB), and a page (4KB).  You cant just "map 4-8 GB on 0-4 GB)". Every memory page in z/arch will have an address. DAT will fixup the page addresses at demand time. So there's no 1:1 mapping between a real memory address and a DAT address - memory is paged in/out in 4KB chunks.

Joe


On Sat, Oct 23, 2021 at 2:38 PM Paul Edwards <mutazilah@...> wrote:
On Sun, Oct 24, 2021 at 06:26 AM, Jesus Antonio wrote:

> "The SIE instruction is IBM patented and licensed technology. Good luck
> with finding information on its operation and details."
>
> Does it mean that I'm not able to utilize such technology without paying
> royalties/getting a license?

Patents only last 20 years. So long as you aren't using any
functionality that didn't exist in the first version of z/Arch,
you can do whatever you want.

> I'm using ESA/390 by the way - However as i mentioned before the
> negative indices problem does not allow me to code for z/Architecture
> correctly.

Even with the negative indexes problem, there is no need
to use ESA/390. You can simply use AM31 in z/Arch instead
(ie don't BSM to AM64).

But if clang doesn't fix the problem for you, you might like to
try seeing if you can activate z/Arch DAT and get the 4 GiB
to 8 GiB virtual address space mapped on to 0 - 4 GiB real
memory. If you can get that to work you get the entire 4 GiB
region, even with negative indexes.

BFN. Paul.






Paul Edwards
 

On Sun, Oct 24, 2021 at 06:44 AM, Joe Monk wrote:

"Patents only last 20 years. So long as you aren't using any
functionality that didn't exist in the first version of z/Arch,
you can do whatever you want."

Every time they come out with a new model of z/box, its a new patent
iteration.
For any new functionality, yes. So long as you stick to the
original functionality that is more than 20 years old, IBM
has no case against you. That's the whole point of the
expiry date. Otherwise at the 19 year mark, people could
just paint their invention a new color and say the patent of
the old version, even with the old color, is renewed for
another 20 years too.

"get the 4 GiB
to 8 GiB virtual address space mapped on to 0 - 4 GiB real
memory."

DAT doesnt work that way.

z/Arch memory in DAT is broken into 3 parts: a region (2GB), a segment
(1MB), and a page (4KB). You cant just "map 4-8 GB on 0-4 GB)". Every
memory page in z/arch will have an address. DAT will fixup the page
addresses at demand time. So there's no 1:1 mapping between a real memory
address and a DAT address - memory is paged in/out in 4KB chunks.
I'm talking about creating page tables so that every 4KB chunk
in the 4 GiB to 8 GiB region is mapped to 0 GiB to 4 GiB.

BFN. Paul.


Joe Monk
 

"I'm talking about creating page tables so that every 4KB chunk
in the 4 GiB to 8 GiB region is mapped to 0 GiB to 4 GiB."

"The pages need not be adjacent in real storage even though assigned to a set of sequential virtual addresses."

So any virtual 4KB page can be placed anywhere in real storage, and that placement is not necessarily contiguous, even through the virtual addresses in the page are contiguous.

Joe



On Sat, Oct 23, 2021 at 3:28 PM Paul Edwards <mutazilah@...> wrote:
On Sun, Oct 24, 2021 at 06:44 AM, Joe Monk wrote:

> "Patents only last 20 years. So long as you aren't using any
> functionality that didn't exist in the first version of z/Arch,
> you can do whatever you want."
>
> Every time they come out with a new model of z/box, its a new patent
> iteration.

For any new functionality, yes. So long as you stick to the
original functionality that is more than 20 years old, IBM
has no case against you. That's the whole point of the
expiry date. Otherwise at the 19 year mark, people could
just paint their invention a new color and say the patent of
the old version, even with the old color, is renewed for
another 20 years too.

> "get the 4 GiB
> to 8 GiB virtual address space mapped on to 0 - 4 GiB real
> memory."
>
> DAT doesnt work that way.
>
> z/Arch memory in DAT is broken into 3 parts: a region (2GB), a segment
> (1MB), and a page (4KB).  You cant just "map 4-8 GB on 0-4 GB)". Every
> memory page in z/arch will have an address. DAT will fixup the page
> addresses at demand time. So there's no 1:1 mapping between a real memory
> address and a DAT address - memory is paged in/out in 4KB chunks.

I'm talking about creating page tables so that every 4KB chunk
in the 4 GiB to 8 GiB region is mapped to 0 GiB to 4 GiB.

BFN. Paul.






Jesus Antonio
 

Hi.


I think what Paul was talking about was the fact that you could be able to remap the higher 4GiB region to be based off 0.

In the sense that 4GiB = 0x0000, 4GiB+4KiB = 0x01000 and henceforth identity map the first 4GiB.

If my understanding is correct this may be doable with two "empty" segments which just remap the higher 4GiB to 0.


However i think this is not allowed and the entire hierarchy has to be created. In that case mapping all the pages for the higher 4GiB space would surely not be optimal.


Adios.

-jesus

On 23/10/21 15:46, Joe Monk wrote:
"I'm talking about creating page tables so that every 4KB chunk
in the 4 GiB to 8 GiB region is mapped to 0 GiB to 4 GiB."

"The pages need not be adjacent in real storage even though assigned to a set of sequential virtual addresses."

So any virtual 4KB page can be placed anywhere in real storage, and that placement is not necessarily contiguous, even through the virtual addresses in the page are contiguous.

Joe



On Sat, Oct 23, 2021 at 3:28 PM Paul Edwards <mutazilah@...> wrote:
On Sun, Oct 24, 2021 at 06:44 AM, Joe Monk wrote:

> "Patents only last 20 years. So long as you aren't using any
> functionality that didn't exist in the first version of z/Arch,
> you can do whatever you want."
>
> Every time they come out with a new model of z/box, its a new patent
> iteration.

For any new functionality, yes. So long as you stick to the
original functionality that is more than 20 years old, IBM
has no case against you. That's the whole point of the
expiry date. Otherwise at the 19 year mark, people could
just paint their invention a new color and say the patent of
the old version, even with the old color, is renewed for
another 20 years too.

> "get the 4 GiB
> to 8 GiB virtual address space mapped on to 0 - 4 GiB real
> memory."
>
> DAT doesnt work that way.
>
> z/Arch memory in DAT is broken into 3 parts: a region (2GB), a segment
> (1MB), and a page (4KB).  You cant just "map 4-8 GB on 0-4 GB)". Every
> memory page in z/arch will have an address. DAT will fixup the page
> addresses at demand time. So there's no 1:1 mapping between a real memory
> address and a DAT address - memory is paged in/out in 4KB chunks.

I'm talking about creating page tables so that every 4KB chunk
in the 4 GiB to 8 GiB region is mapped to 0 GiB to 4 GiB.

BFN. Paul.






Joe Monk
 

"I think what Paul was talking about was the fact that you could be able to remap the higher 4GiB region to be based off 0."

You cant remap the first 8KB. Those are always real addresses, because the CPU has milicode to place certain PSWs at certain addresses during certain events. In IBM OS'es, there are "interrupt handlers", FLIH and SLIH, that work off those addresses. Linux/390 does the same thing.

Joe

On Sat, Oct 23, 2021 at 4:35 PM Jesus Antonio <jesusantonio30122016@...> wrote:

Hi.


I think what Paul was talking about was the fact that you could be able to remap the higher 4GiB region to be based off 0.

In the sense that 4GiB = 0x0000, 4GiB+4KiB = 0x01000 and henceforth identity map the first 4GiB.

If my understanding is correct this may be doable with two "empty" segments which just remap the higher 4GiB to 0.


However i think this is not allowed and the entire hierarchy has to be created. In that case mapping all the pages for the higher 4GiB space would surely not be optimal.


Adios.

-jesus

On 23/10/21 15:46, Joe Monk wrote:
"I'm talking about creating page tables so that every 4KB chunk
in the 4 GiB to 8 GiB region is mapped to 0 GiB to 4 GiB."

"The pages need not be adjacent in real storage even though assigned to a set of sequential virtual addresses."

So any virtual 4KB page can be placed anywhere in real storage, and that placement is not necessarily contiguous, even through the virtual addresses in the page are contiguous.

Joe



On Sat, Oct 23, 2021 at 3:28 PM Paul Edwards <mutazilah@...> wrote:
On Sun, Oct 24, 2021 at 06:44 AM, Joe Monk wrote:

> "Patents only last 20 years. So long as you aren't using any
> functionality that didn't exist in the first version of z/Arch,
> you can do whatever you want."
>
> Every time they come out with a new model of z/box, its a new patent
> iteration.

For any new functionality, yes. So long as you stick to the
original functionality that is more than 20 years old, IBM
has no case against you. That's the whole point of the
expiry date. Otherwise at the 19 year mark, people could
just paint their invention a new color and say the patent of
the old version, even with the old color, is renewed for
another 20 years too.

> "get the 4 GiB
> to 8 GiB virtual address space mapped on to 0 - 4 GiB real
> memory."
>
> DAT doesnt work that way.
>
> z/Arch memory in DAT is broken into 3 parts: a region (2GB), a segment
> (1MB), and a page (4KB).  You cant just "map 4-8 GB on 0-4 GB)". Every
> memory page in z/arch will have an address. DAT will fixup the page
> addresses at demand time. So there's no 1:1 mapping between a real memory
> address and a DAT address - memory is paged in/out in 4KB chunks.

I'm talking about creating page tables so that every 4KB chunk
in the 4 GiB to 8 GiB region is mapped to 0 GiB to 4 GiB.

BFN. Paul.