Date   

Re: no echo

Paul Edwards
 

On Wed, Dec 8, 2021 at 06:57 PM, Paul Edwards wrote:

If SYSIN is RECFM=U then that can be a trigger that PDPCLIB
will echo SYSIN to SYSPRINT, and do line-editing when the
app does a fgets from stdin.
I kludged it for now, just doing that when fgets is called,
but it is enough for proof of concept. I now have both the
command.exe and micro-emacs working great!

There is still an unrelated problem with micro-emacs thinking
double-quote takes up 2 characters on the screen or something.

All source code has been released in the usual places.

BFN. Paul.


Re: no echo

Paul Edwards
 

On Wed, Nov 17, 2021 at 01:36 PM, Paul Edwards wrote:

The problem is with PDOS/3X0 using the MVS read from
file SYSIN which is RECFM=U. This is no longer a file I
need, it's a terminal, so I need the ability to do some sort
of ioctl to switch it from line mode to character mode, and
switch off echo. MVS probably doesn't have a call to do
exactly that, but I might be able to extend a call that does
something else.
I have thought of a solution.

If SYSIN is RECFM=U then that can be a trigger that PDPCLIB
will echo SYSIN to SYSPRINT, and do line-editing when the
app does a fgets from stdin.

But if the app does a setvbuf no-buffering then this echo is
switched off.

Take the burden away from the OS and into the C library.

BFN. Paul.


no echo

Paul Edwards
 

I was thinking that MSDOS needed an extra call so that
when setvbuf no-buffering of stdin was done, it could be
informed that we're switching to no echo. But now I think
it is good enough that the C library makes the switch to
the no-echo API call to retrieve a character. If MSDOS
needs to do something special it can.

The problem is with PDOS/3X0 using the MVS read from
file SYSIN which is RECFM=U. This is no longer a file I
need, it's a terminal, so I need the ability to do some sort
of ioctl to switch it from line mode to character mode, and
switch off echo. MVS probably doesn't have a call to do
exactly that, but I might be able to extend a call that does
something else. Do MVS programs ever modify a DCB
or something like that? There's a TRKCALC which is
along those lines. Do I need to create a special DEB or
something?

Thanks. Paul.


Re: z/Architecture?

Joe Monk
 

"I think what Paul was talking about was the fact that you could be able to remap the higher 4GiB region to be based off 0."

You cant remap the first 8KB. Those are always real addresses, because the CPU has milicode to place certain PSWs at certain addresses during certain events. In IBM OS'es, there are "interrupt handlers", FLIH and SLIH, that work off those addresses. Linux/390 does the same thing.

Joe

On Sat, Oct 23, 2021 at 4:35 PM Jesus Antonio <jesusantonio30122016@...> wrote:

Hi.


I think what Paul was talking about was the fact that you could be able to remap the higher 4GiB region to be based off 0.

In the sense that 4GiB = 0x0000, 4GiB+4KiB = 0x01000 and henceforth identity map the first 4GiB.

If my understanding is correct this may be doable with two "empty" segments which just remap the higher 4GiB to 0.


However i think this is not allowed and the entire hierarchy has to be created. In that case mapping all the pages for the higher 4GiB space would surely not be optimal.


Adios.

-jesus

On 23/10/21 15:46, Joe Monk wrote:
"I'm talking about creating page tables so that every 4KB chunk
in the 4 GiB to 8 GiB region is mapped to 0 GiB to 4 GiB."

"The pages need not be adjacent in real storage even though assigned to a set of sequential virtual addresses."

So any virtual 4KB page can be placed anywhere in real storage, and that placement is not necessarily contiguous, even through the virtual addresses in the page are contiguous.

Joe



On Sat, Oct 23, 2021 at 3:28 PM Paul Edwards <mutazilah@...> wrote:
On Sun, Oct 24, 2021 at 06:44 AM, Joe Monk wrote:

> "Patents only last 20 years. So long as you aren't using any
> functionality that didn't exist in the first version of z/Arch,
> you can do whatever you want."
>
> Every time they come out with a new model of z/box, its a new patent
> iteration.

For any new functionality, yes. So long as you stick to the
original functionality that is more than 20 years old, IBM
has no case against you. That's the whole point of the
expiry date. Otherwise at the 19 year mark, people could
just paint their invention a new color and say the patent of
the old version, even with the old color, is renewed for
another 20 years too.

> "get the 4 GiB
> to 8 GiB virtual address space mapped on to 0 - 4 GiB real
> memory."
>
> DAT doesnt work that way.
>
> z/Arch memory in DAT is broken into 3 parts: a region (2GB), a segment
> (1MB), and a page (4KB).  You cant just "map 4-8 GB on 0-4 GB)". Every
> memory page in z/arch will have an address. DAT will fixup the page
> addresses at demand time. So there's no 1:1 mapping between a real memory
> address and a DAT address - memory is paged in/out in 4KB chunks.

I'm talking about creating page tables so that every 4KB chunk
in the 4 GiB to 8 GiB region is mapped to 0 GiB to 4 GiB.

BFN. Paul.






Re: z/Architecture?

Jesus Antonio
 

Hi.


I think what Paul was talking about was the fact that you could be able to remap the higher 4GiB region to be based off 0.

In the sense that 4GiB = 0x0000, 4GiB+4KiB = 0x01000 and henceforth identity map the first 4GiB.

If my understanding is correct this may be doable with two "empty" segments which just remap the higher 4GiB to 0.


However i think this is not allowed and the entire hierarchy has to be created. In that case mapping all the pages for the higher 4GiB space would surely not be optimal.


Adios.

-jesus

On 23/10/21 15:46, Joe Monk wrote:
"I'm talking about creating page tables so that every 4KB chunk
in the 4 GiB to 8 GiB region is mapped to 0 GiB to 4 GiB."

"The pages need not be adjacent in real storage even though assigned to a set of sequential virtual addresses."

So any virtual 4KB page can be placed anywhere in real storage, and that placement is not necessarily contiguous, even through the virtual addresses in the page are contiguous.

Joe



On Sat, Oct 23, 2021 at 3:28 PM Paul Edwards <mutazilah@...> wrote:
On Sun, Oct 24, 2021 at 06:44 AM, Joe Monk wrote:

> "Patents only last 20 years. So long as you aren't using any
> functionality that didn't exist in the first version of z/Arch,
> you can do whatever you want."
>
> Every time they come out with a new model of z/box, its a new patent
> iteration.

For any new functionality, yes. So long as you stick to the
original functionality that is more than 20 years old, IBM
has no case against you. That's the whole point of the
expiry date. Otherwise at the 19 year mark, people could
just paint their invention a new color and say the patent of
the old version, even with the old color, is renewed for
another 20 years too.

> "get the 4 GiB
> to 8 GiB virtual address space mapped on to 0 - 4 GiB real
> memory."
>
> DAT doesnt work that way.
>
> z/Arch memory in DAT is broken into 3 parts: a region (2GB), a segment
> (1MB), and a page (4KB).  You cant just "map 4-8 GB on 0-4 GB)". Every
> memory page in z/arch will have an address. DAT will fixup the page
> addresses at demand time. So there's no 1:1 mapping between a real memory
> address and a DAT address - memory is paged in/out in 4KB chunks.

I'm talking about creating page tables so that every 4KB chunk
in the 4 GiB to 8 GiB region is mapped to 0 GiB to 4 GiB.

BFN. Paul.






Re: z/Architecture?

Joe Monk
 

"I'm talking about creating page tables so that every 4KB chunk
in the 4 GiB to 8 GiB region is mapped to 0 GiB to 4 GiB."

"The pages need not be adjacent in real storage even though assigned to a set of sequential virtual addresses."

So any virtual 4KB page can be placed anywhere in real storage, and that placement is not necessarily contiguous, even through the virtual addresses in the page are contiguous.

Joe



On Sat, Oct 23, 2021 at 3:28 PM Paul Edwards <mutazilah@...> wrote:
On Sun, Oct 24, 2021 at 06:44 AM, Joe Monk wrote:

> "Patents only last 20 years. So long as you aren't using any
> functionality that didn't exist in the first version of z/Arch,
> you can do whatever you want."
>
> Every time they come out with a new model of z/box, its a new patent
> iteration.

For any new functionality, yes. So long as you stick to the
original functionality that is more than 20 years old, IBM
has no case against you. That's the whole point of the
expiry date. Otherwise at the 19 year mark, people could
just paint their invention a new color and say the patent of
the old version, even with the old color, is renewed for
another 20 years too.

> "get the 4 GiB
> to 8 GiB virtual address space mapped on to 0 - 4 GiB real
> memory."
>
> DAT doesnt work that way.
>
> z/Arch memory in DAT is broken into 3 parts: a region (2GB), a segment
> (1MB), and a page (4KB).  You cant just "map 4-8 GB on 0-4 GB)". Every
> memory page in z/arch will have an address. DAT will fixup the page
> addresses at demand time. So there's no 1:1 mapping between a real memory
> address and a DAT address - memory is paged in/out in 4KB chunks.

I'm talking about creating page tables so that every 4KB chunk
in the 4 GiB to 8 GiB region is mapped to 0 GiB to 4 GiB.

BFN. Paul.






Re: z/Architecture?

Paul Edwards
 

On Sun, Oct 24, 2021 at 06:44 AM, Joe Monk wrote:

"Patents only last 20 years. So long as you aren't using any
functionality that didn't exist in the first version of z/Arch,
you can do whatever you want."

Every time they come out with a new model of z/box, its a new patent
iteration.
For any new functionality, yes. So long as you stick to the
original functionality that is more than 20 years old, IBM
has no case against you. That's the whole point of the
expiry date. Otherwise at the 19 year mark, people could
just paint their invention a new color and say the patent of
the old version, even with the old color, is renewed for
another 20 years too.

"get the 4 GiB
to 8 GiB virtual address space mapped on to 0 - 4 GiB real
memory."

DAT doesnt work that way.

z/Arch memory in DAT is broken into 3 parts: a region (2GB), a segment
(1MB), and a page (4KB). You cant just "map 4-8 GB on 0-4 GB)". Every
memory page in z/arch will have an address. DAT will fixup the page
addresses at demand time. So there's no 1:1 mapping between a real memory
address and a DAT address - memory is paged in/out in 4KB chunks.
I'm talking about creating page tables so that every 4KB chunk
in the 4 GiB to 8 GiB region is mapped to 0 GiB to 4 GiB.

BFN. Paul.


Re: z/Architecture?

Joe Monk
 

"Patents only last 20 years. So long as you aren't using any
functionality that didn't exist in the first version of z/Arch,
you can do whatever you want."

Every time they come out with a new model of z/box, its a new patent iteration.

"get the 4 GiB
to 8 GiB virtual address space mapped on to 0 - 4 GiB real
memory."

DAT doesnt work that way.

z/Arch memory in DAT is broken into 3 parts: a region (2GB), a segment (1MB), and a page (4KB).  You cant just "map 4-8 GB on 0-4 GB)". Every memory page in z/arch will have an address. DAT will fixup the page addresses at demand time. So there's no 1:1 mapping between a real memory address and a DAT address - memory is paged in/out in 4KB chunks.

Joe


On Sat, Oct 23, 2021 at 2:38 PM Paul Edwards <mutazilah@...> wrote:
On Sun, Oct 24, 2021 at 06:26 AM, Jesus Antonio wrote:

> "The SIE instruction is IBM patented and licensed technology. Good luck
> with finding information on its operation and details."
>
> Does it mean that I'm not able to utilize such technology without paying
> royalties/getting a license?

Patents only last 20 years. So long as you aren't using any
functionality that didn't exist in the first version of z/Arch,
you can do whatever you want.

> I'm using ESA/390 by the way - However as i mentioned before the
> negative indices problem does not allow me to code for z/Architecture
> correctly.

Even with the negative indexes problem, there is no need
to use ESA/390. You can simply use AM31 in z/Arch instead
(ie don't BSM to AM64).

But if clang doesn't fix the problem for you, you might like to
try seeing if you can activate z/Arch DAT and get the 4 GiB
to 8 GiB virtual address space mapped on to 0 - 4 GiB real
memory. If you can get that to work you get the entire 4 GiB
region, even with negative indexes.

BFN. Paul.






Re: z/Architecture?

Joe Monk
 

"Does it mean that I'm not able to utilize such technology without paying royalties/getting a license?"

Depends on how badly you infringe the patent! :)


Joe


On Sat, Oct 23, 2021 at 2:26 PM Jesus Antonio <jesusantonio30122016@...> wrote:

Hi.


"The SIE instruction is IBM patented and licensed technology. Good luck with finding information on its operation and details."

Does it mean that I'm not able to utilize such technology without paying royalties/getting a license?


"Do you have interrupts enabled for the CPU timer? Bit 53 of control register 0 must be 1."

Yes, I made the PSW be set to allow CPU timers and i set the appropriate bits on CR0 as well.


I'm using ESA/390 by the way - However as i mentioned before the negative indices problem does not allow me to code for z/Architecture correctly.


Adios.

-jesus

On 23/10/21 13:36, Joe Monk wrote:
"I have recently taken interest in going further to develop UDOS into a 
more wide scope. This is by allowing UDOS to act as a hypervisor for 
let's say running z/OS under a VM and z/Linux too."

The SIE instruction is IBM patented and licensed technology. Good luck with finding information on its operation and details.

"Another question: Modifying IBM millicode

Achievable or outright impossible? I've heard it's not possible but i 
may be wrong."

Not possible without physical access to the Hardware Support Element (a pair of 1U servers that are physically located inside the machine).

"How to drive the timer?

I'm trying to activate the timer, I'm using the SET TIMER and STORE 
timer instructions and set it to a positive value that should generate 
an external interrupt once it goes to the negative. But no external 
interruption is recognized - what am i doing wrong?"

Do you have interrupts enabled for the CPU timer? Bit 53 of control register 0 must be 1.

Joe

On Sat, Oct 23, 2021 at 12:37 PM Jesus Antonio <jesusantonio30122016@...> wrote:
Hi.


As I'm writing this I'm compiling the latest version of clang in hopes
of circumventing the z/Architecture negative indexes code generation
"bug" present on the GCC compiler. I also want to avoid the EBCDIC
formatting problems present on GCC. Hopefully i can use EBCDIC normally
without any barriers (such as spurious warnings).


Now for the main question: z/Architecture Hypervisor and Virtualization
Technologies

I have recently taken interest in going further to develop UDOS into a
more wide scope. This is by allowing UDOS to act as a hypervisor for
let's say running z/OS under a VM and z/Linux too.

How can i accomplish this task, what hypervisor functionality i need? Is
this even achievable?


Another question: Modifying IBM millicode

Achievable or outright impossible? I've heard it's not possible but i
may be wrong.


How to drive the timer?

I'm trying to activate the timer, I'm using the SET TIMER and STORE
timer instructions and set it to a positive value that should generate
an external interrupt once it goes to the negative. But no external
interruption is recognized - what am i doing wrong?


Adios.

- jesus







Re: z/Architecture?

Paul Edwards
 

On Sun, Oct 24, 2021 at 06:26 AM, Jesus Antonio wrote:

"The SIE instruction is IBM patented and licensed technology. Good luck
with finding information on its operation and details."

Does it mean that I'm not able to utilize such technology without paying
royalties/getting a license?
Patents only last 20 years. So long as you aren't using any
functionality that didn't exist in the first version of z/Arch,
you can do whatever you want.

I'm using ESA/390 by the way - However as i mentioned before the
negative indices problem does not allow me to code for z/Architecture
correctly.
Even with the negative indexes problem, there is no need
to use ESA/390. You can simply use AM31 in z/Arch instead
(ie don't BSM to AM64).

But if clang doesn't fix the problem for you, you might like to
try seeing if you can activate z/Arch DAT and get the 4 GiB
to 8 GiB virtual address space mapped on to 0 - 4 GiB real
memory. If you can get that to work you get the entire 4 GiB
region, even with negative indexes.

BFN. Paul.


Re: z/Architecture?

Jesus Antonio
 

Hi.


"The SIE instruction is IBM patented and licensed technology. Good luck with finding information on its operation and details."

Does it mean that I'm not able to utilize such technology without paying royalties/getting a license?


"Do you have interrupts enabled for the CPU timer? Bit 53 of control register 0 must be 1."

Yes, I made the PSW be set to allow CPU timers and i set the appropriate bits on CR0 as well.


I'm using ESA/390 by the way - However as i mentioned before the negative indices problem does not allow me to code for z/Architecture correctly.


Adios.

-jesus

On 23/10/21 13:36, Joe Monk wrote:
"I have recently taken interest in going further to develop UDOS into a 
more wide scope. This is by allowing UDOS to act as a hypervisor for 
let's say running z/OS under a VM and z/Linux too."

The SIE instruction is IBM patented and licensed technology. Good luck with finding information on its operation and details.

"Another question: Modifying IBM millicode

Achievable or outright impossible? I've heard it's not possible but i 
may be wrong."

Not possible without physical access to the Hardware Support Element (a pair of 1U servers that are physically located inside the machine).

"How to drive the timer?

I'm trying to activate the timer, I'm using the SET TIMER and STORE 
timer instructions and set it to a positive value that should generate 
an external interrupt once it goes to the negative. But no external 
interruption is recognized - what am i doing wrong?"

Do you have interrupts enabled for the CPU timer? Bit 53 of control register 0 must be 1.

Joe

On Sat, Oct 23, 2021 at 12:37 PM Jesus Antonio <jesusantonio30122016@...> wrote:
Hi.


As I'm writing this I'm compiling the latest version of clang in hopes
of circumventing the z/Architecture negative indexes code generation
"bug" present on the GCC compiler. I also want to avoid the EBCDIC
formatting problems present on GCC. Hopefully i can use EBCDIC normally
without any barriers (such as spurious warnings).


Now for the main question: z/Architecture Hypervisor and Virtualization
Technologies

I have recently taken interest in going further to develop UDOS into a
more wide scope. This is by allowing UDOS to act as a hypervisor for
let's say running z/OS under a VM and z/Linux too.

How can i accomplish this task, what hypervisor functionality i need? Is
this even achievable?


Another question: Modifying IBM millicode

Achievable or outright impossible? I've heard it's not possible but i
may be wrong.


How to drive the timer?

I'm trying to activate the timer, I'm using the SET TIMER and STORE
timer instructions and set it to a positive value that should generate
an external interrupt once it goes to the negative. But no external
interruption is recognized - what am i doing wrong?


Adios.

- jesus







Re: z/Architecture?

Joe Monk
 

"I have recently taken interest in going further to develop UDOS into a 
more wide scope. This is by allowing UDOS to act as a hypervisor for 
let's say running z/OS under a VM and z/Linux too."

The SIE instruction is IBM patented and licensed technology. Good luck with finding information on its operation and details.

"Another question: Modifying IBM millicode

Achievable or outright impossible? I've heard it's not possible but i 
may be wrong."

Not possible without physical access to the Hardware Support Element (a pair of 1U servers that are physically located inside the machine).

"How to drive the timer?

I'm trying to activate the timer, I'm using the SET TIMER and STORE 
timer instructions and set it to a positive value that should generate 
an external interrupt once it goes to the negative. But no external 
interruption is recognized - what am i doing wrong?"

Do you have interrupts enabled for the CPU timer? Bit 53 of control register 0 must be 1.

Joe

On Sat, Oct 23, 2021 at 12:37 PM Jesus Antonio <jesusantonio30122016@...> wrote:
Hi.


As I'm writing this I'm compiling the latest version of clang in hopes
of circumventing the z/Architecture negative indexes code generation
"bug" present on the GCC compiler. I also want to avoid the EBCDIC
formatting problems present on GCC. Hopefully i can use EBCDIC normally
without any barriers (such as spurious warnings).


Now for the main question: z/Architecture Hypervisor and Virtualization
Technologies

I have recently taken interest in going further to develop UDOS into a
more wide scope. This is by allowing UDOS to act as a hypervisor for
let's say running z/OS under a VM and z/Linux too.

How can i accomplish this task, what hypervisor functionality i need? Is
this even achievable?


Another question: Modifying IBM millicode

Achievable or outright impossible? I've heard it's not possible but i
may be wrong.


How to drive the timer?

I'm trying to activate the timer, I'm using the SET TIMER and STORE
timer instructions and set it to a positive value that should generate
an external interrupt once it goes to the negative. But no external
interruption is recognized - what am i doing wrong?


Adios.

- jesus







Re: Pascal

Joe Monk
 

"But in the long term I don't want to map the 4 GiB
to 8 GiB region onto the 0 - 4 GiB region as that is a kludge."

Thats not how DAT works on z/Arch.

Joe

On Sat, Oct 23, 2021 at 1:01 PM Paul Edwards <mutazilah@...> wrote:
On Sun, Oct 24, 2021 at 04:47 AM, Joe Monk wrote:

>> Right, so the negative index, typically -1, adds a whopping
>> 4 GiB to my address, putting it into the 4 GiB - 8 GiB range
>> where there is no memory present, and thus it crashes.
>
> Why isnt there memory there? DAT takes care of this mapping.

That's a really good idea. That will indeed solve my immediate
problem. But in the long term I don't want to map the 4 GiB
to 8 GiB region onto the 0 - 4 GiB region as that is a kludge.
I want the compiler to generate the code I want. And I want to
run with DAT off (as now), and be able to load 64-bit programs
into the 4 GiB to 8 GiB virtual region instead of having a hole.

But yes, I'll pencil this in as something to do in the short term,
to replace my other solution of using AM31 in z/Arch.

BFN. Paul.






Re: Pascal

Paul Edwards
 

On Sun, Oct 24, 2021 at 04:47 AM, Joe Monk wrote:

Right, so the negative index, typically -1, adds a whopping
4 GiB to my address, putting it into the 4 GiB - 8 GiB range
where there is no memory present, and thus it crashes.
Why isnt there memory there? DAT takes care of this mapping.
That's a really good idea. That will indeed solve my immediate
problem. But in the long term I don't want to map the 4 GiB
to 8 GiB region onto the 0 - 4 GiB region as that is a kludge.
I want the compiler to generate the code I want. And I want to
run with DAT off (as now), and be able to load 64-bit programs
into the 4 GiB to 8 GiB virtual region instead of having a hole.

But yes, I'll pencil this in as something to do in the short term,
to replace my other solution of using AM31 in z/Arch.

BFN. Paul.


Re: Pascal

Joe Monk
 

"Right, so the negative index, typically -1, adds a whopping
4 GiB to my address, putting it into the 4 GiB - 8 GiB range
where there is no memory present, and thus it crashes."

Why isnt there memory there? DAT takes care of this mapping.

Joe

On Sat, Oct 23, 2021 at 12:41 PM Paul Edwards <mutazilah@...> wrote:
On Sun, Oct 24, 2021 at 04:36 AM, Joe Monk wrote:

> "The z/Arch quote talks of AM31. I'm running AM64."
>
> z/arch PrincOps says: "Unsigned binary arithmetic is used in address
> arithmetic for adding the X, B, and D fields."

Right, so the negative index, typically -1, adds a whopping
4 GiB to my address, putting it into the 4 GiB - 8 GiB range
where there is no memory present, and thus it crashes.

BFN. Paul.






Re: Pascal

Paul Edwards
 

On Sun, Oct 24, 2021 at 04:36 AM, Joe Monk wrote:

"The z/Arch quote talks of AM31. I'm running AM64."

z/arch PrincOps says: "Unsigned binary arithmetic is used in address
arithmetic for adding the X, B, and D fields."
Right, so the negative index, typically -1, adds a whopping
4 GiB to my address, putting it into the 4 GiB - 8 GiB range
where there is no memory present, and thus it crashes.

BFN. Paul.


z/Architecture?

Jesus Antonio
 

Hi.


As I'm writing this I'm compiling the latest version of clang in hopes of circumventing the z/Architecture negative indexes code generation "bug" present on the GCC compiler. I also want to avoid the EBCDIC formatting problems present on GCC. Hopefully i can use EBCDIC normally without any barriers (such as spurious warnings).


Now for the main question: z/Architecture Hypervisor and Virtualization Technologies

I have recently taken interest in going further to develop UDOS into a more wide scope. This is by allowing UDOS to act as a hypervisor for let's say running z/OS under a VM and z/Linux too.

How can i accomplish this task, what hypervisor functionality i need? Is this even achievable?


Another question: Modifying IBM millicode

Achievable or outright impossible? I've heard it's not possible but i may be wrong.


How to drive the timer?

I'm trying to activate the timer, I'm using the SET TIMER and STORE timer instructions and set it to a positive value that should generate an external interrupt once it goes to the negative. But no external interruption is recognized - what am i doing wrong?


Adios.

- jesus


Re: Pascal

Joe Monk
 

"The z/Arch quote talks of AM31. I'm running AM64."

z/arch PrincOps says: "Unsigned binary arithmetic is used in address arithmetic for adding the X, B, and D fields."

Joe


On Sat, Oct 23, 2021 at 5:33 AM Paul Edwards <mutazilah@...> wrote:
On Sat, Oct 23, 2021 at 09:29 PM, Joe Monk wrote:

> So, I am confused. Every PrincOps manual I can find says that a negative
> index in a register is irrelevant because the sign bit is ignored. So, how
> is this affecting you?

The z/Arch quote talks of AM31. I'm running AM64.

BFN. Paul.






VM/SP

Turgut Kalfaoglu
 

Hi - I am not sure if this is the correct forum, but I had a question that had me stumped ..

When I type ID, I get

MAINT AT TRVM1 VIA *   (date)  (time)

instead of VIA RSCS.. that causes problems for the TELL and I assume SENDFILE commands.. Any ideas how to replace that asterisk with something meaningful?

Many thanks :)

-t



Re: Pascal

Paul Edwards
 

On Sat, Oct 23, 2021 at 09:29 PM, Joe Monk wrote:

So, I am confused. Every PrincOps manual I can find says that a negative
index in a register is irrelevant because the sign bit is ignored. So, how
is this affecting you?
The z/Arch quote talks of AM31. I'm running AM64.

BFN. Paul.

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