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I/O Waveform Questions


 

A couple questions, if I may, guys?  I'm studying Mike Riley's I/O logic and his IDE/ATA interface and I'm trying to translate it to fit the constraints of the CLC (Configurable Logic Cell) logic available in my PIC microcontroller.
 
(1) Will the CLC logic in the diagram below generate the desired 'core' waveforms shown in that diagram?
 
(2) Why is Mike (Riley) qualifying I/O transactions to a waveform that begins at the falling edge of 'TPA' and ends at the falling edge of 'TPB'?  I understand why you need to go to the end of 'TPB'.  Is it because the 'N' lines become valid during clock 0 of the machine cycle and the 'MRD' line may change during clock 1 of the machine cycle and it's somehow safer to wait until after 'TPA' (beginning of clock 2)?
 
Thanks in advance.  Cheerful regards, Mike, K8LH
 



Mike Riley
 

Been a long time since I designed that circuit, but what seems to stick in my mind, for the read operation, the 1802 provides the MWR signal to write the databus content's to ram after the trailing edge of TPA and raises MWR at the trailing edge of TPB, therefore the RD signal generated by my logic allows the data to be stable on the database until after the MWR pulse is complete for the write to memory of the INPutted data.  By starting the RD signal at the end of TPA then there is plenty of time for the io device to have the data ready and stable on the databus by the time MWR occurs.

For the out operation the write strobe from the 1802 (combination of MRD, TPB and the N lines) produces a pulse that is the same width as TPB.  At the start of TPB the data from memory is stable on the database so when WR goes low  the data is stable to write to the device.  The IDE clocks data on the falling edge of the WR.  So on the leading edge of TP the data is ready to be strobed to the output device, that data is only stable until the end of TPB.

Hopefully this makes some sense?
    Mike



From: cosmacelf@groups.io <cosmacelf@groups.io> on behalf of Mike McLaren, K8LH <k8lh@...>
Sent: Saturday, August 8, 2020 10:04 AM
To: cosmacelf <cosmacelf@groups.io>
Subject: [cosmacelf] I/O Waveform Questions
 
A couple questions, if I may, guys?  I'm studying Mike Riley's I/O logic and his IDE/ATA interface and I'm trying to translate it to fit the constraints of the CLC (Configurable Logic Cell) logic available in my PIC microcontroller.
 
(1) Will the CLC logic in the diagram below generate the desired 'core' waveforms shown in that diagram?
 
(2) Why is Mike (Riley) qualifying I/O transactions to a waveform that begins at the falling edge of 'TPA' and ends at the falling edge of 'TPB'?  I understand why you need to go to the end of 'TPB'.  Is it because the 'N' lines become valid during clock 0 of the machine cycle and the 'MRD' line may change during clock 1 of the machine cycle and it's somehow safer to wait until after 'TPA' (beginning of clock 2)?
 
Thanks in advance.  Cheerful regards, Mike, K8LH
 



 

Thank you for the explanation, Mike.  That's a very clever way to increase the I/O /RD pulse width compared to using the /MWR signal as the I/O /RD signal, which is only 2 clock cycles wide.

Do you think I would experience problems with the IDE/ATA interface if I try to use the /MWR signal for my /INP (/RD) signal?  It would simplify my CLC logic and allow for up to 7 configurable I/O channel lines.




Mike Riley
 

Mike, No, more than likely using MWR for your INP will not work and here is why.  In the 1802, I/O does not work the same as it does in other cpus, in most cpus an INP operation would take data from the data bus and write it into an internal register.  In the 1802 the cpu performs a memory write cycle to write the data to memory instead.  The data must be on the data bus and stable BEFORE the leading edge of MWR and remain stable until the trailing edge of MWR.  If you were to use MWR as your INP signal then if the memory being used acts on the leading edge of MWR then the data is not on the data bus to be written since the I/O device would not be making its data available on the data bus at the same time as the actual write signal, but a short time afterwards, remember it takes a certain amount of time for a device to make data available from the time it receives a RD request to output the data.  That time is not very long, certainly way less than a clock pulse in many cases, but even if it were 100ns that would be too late for the MWR pulse being given to the memory which expects the data bus to have the data stable when MWR is asserted.  At the very least your INP would have to be at least 1 clock earlier than MWR, and depending on the I/O device, this may not be enough time before MWR begins.
     Mike



From: cosmacelf@groups.io <cosmacelf@groups.io> on behalf of Mike McLaren, K8LH <k8lh@...>
Sent: Saturday, August 8, 2020 8:29 PM
To: cosmacelf@groups.io <cosmacelf@groups.io>
Subject: Re: [cosmacelf] I/O Waveform Questions
 

Thank you for the explanation, Mike.  That's a very clever way to increase the I/O /RD pulse width compared to using the /MWR signal as the I/O /RD signal, which is only 2 clock cycles wide.

Do you think I would experience problems with the IDE/ATA interface if I try to use the /MWR signal for my /INP (/RD) signal?  It would simplify my CLC logic and allow for up to 7 configurable I/O channel lines.




ian may
 

Mike McLaren - the last page of the RCA CDP1852 data sheet describes the reason why you might want to generate the signal you have called "SEL" in your circuit (which goes high on the falling edge of TPA and low on the falling edge of TPB) . As you wrote, the issue is that the N lines become valid before /MRD is valid.

Consider the case of generating an INP signal from "N lines non-zero" and /MRD high and an OUT signal from "N lines non-zero" and /MRD low. For every OUT instruction there would be a spurious INP signal generated due to the time delay between the N lines being non-zero and /MRD still being high before it goes low. If that spurious INP were to read the data port of a UART (for example) you could lose a received character.

/MRD is valid by the falling edge of TPA, so if INP is generated from "N lines non-zero" AND /MRD high AND "SEL" high a spurious read won't happen. OUT can be generated by "N lines non-zero" AND /MRD low AND "SEL" high. This system would produce INP and OUT pulses of approximately 5.5 clock cycles (the time between the falling edge of TPA and the falling edge of TPB).

Mike Riley has used (in his "Port Extender" and "Pico/Elf" circuits) the RCA standard "N lines non-zero" AND /MRD low AND TPB high to generate OUT, which is fine for most peripherals at normal 1802 clock speeds. I like to run my 1802s at higher clock speeds, so generating OUT from TPB could result in the maximum clock speed being set by the speed of a peripheral rather than the limit of the particular 1802 in use. I therefore prefer the 5.5 clock cycle OUT generation approach when pushing clock frequencies higher than specifications.
Cheers, Ian.


 
Edited

Ian, Mike, and gang:  Thanks for the input.  Ian, I think I'll have the I/O subsystem automatically use the longer (5.5 cycle) 'SEL' waveform for the INP/OUT strobes whenever the user selects a CPU clock greater than 4.0-MHz.

I'd also like to try using that 'SEL' waveform instead of 'TPB' as the 'E' or 'Φ2' clock for my HD63B50 ACIA or other 6800/6500 peripheral ICs.  I believe it may allow me to run those peripheral ICs with an 8-MHz CPU clock.