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CDP18S651 Microboard and 3.5 SONY MPF920 Drives #Homebrew #microboards


Jeff Truck
 

Has anyone out there been able to get a '651 style microboard to work successfully with a SONY 3.5 drive?   I've attempted to recreate the '651 board.   For the most part, it works.   Small little code fragments which interact with the drive, such as Sense Drive Status, Obtain Version of the UPD765 FDC, Read Main Status, Read Result Registers, etc.   The one thing I can't get to work is a Format Track operation.  I've got a small army of probes hooked up to various logic lines and the hunt continues as to what the culprit might be, but I thought to ask the crew here to find out if someone has already gone down this path and discovered something about the newer drives or perhaps it's the fact that the 1802 is running at 4MHz - who knows.

Result Status 01 comes back with OVERRUN set which implies that the DMA request to obtain from the main system a list of C, H, R and N values is not being serviced.   I've tried to ensure that the proper DMA channel set up and number of DMA blocks is set up appropriately.   I'm still digging away at this.

You will find a picture of the new board in my photo album.
 
Jeff


ajparent1/kb1gmx <kb1gmx@...>
 

Jeff,
 Over run indicated that DMA did not service the request.
Recent memory says the 651 board has a SMA configuration register of
some sort to set read or write DMA depending on the desired operation.

CHRN are values supplied during Comand phase (for read write and others)
and it is supplied for each sector of the FORMAT command.

You really need to be familiar with the 765 and kin as nothing will make
sense otherwise.  Doesn't help that RCA was rather obscure on the boards
operation.

Allison
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Jeff Truck
 

Allison,

Your recent memory is correct - the 651 board utilizes an OUT4 instruction to set up the DMA activity, direction, motor on, etc.    It's followed by an OUT7 instruction to specify the number of 128 byte blocks to fetch during the DMA activity.   The CHRN values are fetched via the subsequent DMA out by the 651 as a result of the format command being carried out, presumably after the mandatory command arguments for head and unit, bytes/sector, sectors/track, GAP3 length and the filler byte were sent as well.   

It's just a matter of time before I figure out where the flaw lies.   I just wanted to make sure that the latest generation of floppy drives (even though they are nearly 20 years old) didn't have some quirk.  The signal lines between them and the board remain somewhat stable.  I've dug up more documentation then I care to have collected in my quest for the answer.   

I'm waiting for a bigger logic analyzer to arrive tomorrow - my 8 line one doesn't cut it.   

Jeff


David Schultz
 

On 5/30/20 1:16 PM, Jeff Truck wrote:

Result Status 01 comes back with OVERRUN set which implies that the DMA
request to obtain from the main system a list of C, H, R and N values is
not being serviced.   I've tried to ensure that the proper DMA channel
set up and number of DMA blocks is set up appropriately.   I'm still
digging away at this.
Have you looked at the MicroDOS format command?



stxd ; head/drive select byte
ldi 4Dh ; format track command (MFM mode)
stxd
ldi 01 ; BYTECNT
stxd
ldi DMAO ; DMASEL
str r7
ldi 06
plo r8

call CMDS
call WAITS


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Jeff Truck
 

David.

Yes - I've been looking at that along with other commands.  

I've written a small diagnostic script just to keep things as simple as possible versus attempting on getting something like MicroDOS to run.   I've attached the listing and a session log from it's output in case you or anyone else would care to examine what I am doing software wise.

Jeff


taf123
 

Hi Jeff -

I used both a Sony MPF920 and a TEAC FD235HF-6529 with my FDC board which is based upon the '651, but uses the FDC9266, which is basically a '765 and data separator in one package to simplify the build.

I did have to modify pin 34 of the MPF920 so it would present a READY signal instead of the Disk Change signal PC's prefer.

See https://groups.io/g/cosmacelf/topic/todd_s_elf_ish_to_get_an_fdc/61877282 for all of the gory details.

Note that I'm only running the ELF-ish at 2.5Mhz.

Best regards,
Todd


Jeff Truck
 

Todd,

Thank you - I'm going to re-read everything in that long posting of accumulated information.

I'm hitting myself figuratively on the head when announcing the fact that I discovered last night the problem.   I have a video card and it's design assumed that the only circuit concerned about / connected to the DMA-OUT signal was the video card.  The video card ties DMA-OUT directly to an EEPROM output.   So, this entire time the FDC board was wanting to bring DMA-OUT low, but my video card felt different about it.   Remove the video card - wow - nine little pulses of DMA-OUT going low for every track.   Little stupid things like this only help to cement the concepts of bus management in my head.

Jeff


ajparent1/kb1gmx <kb1gmx@...>
 

Jeff,

With the 765 [also its kin] its important to note the distinct difference between command phase
with its parameters and DATA phase.

Yes getting floppies going is a pain, especially oddball units.  Some things that
RCA did made it more obscure.

Allison
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ajparent1/kb1gmx <kb1gmx@...>
 

Todd,

I'm one to always for that pin to ready. its one less thing in the early stages 
to get in the way.  one pull up resistor and its good.

For some OSs having ready is at most useless and some drives what it
means by ready is also useless.  For first up system simplifying the interface
really helps get the show running.  

You would not believe how much can be left out and work well.

Allison
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cellarcat
 

Jeff, Todd and I have both been running 300 rpm drives instead of the 600 rpm Sony. I actually have one of those early beasts but I could never get it to work. I did get a Gotek running as a simulated 600 rpm drive. Currently I am using 2 720k 80 track quad 5.25 inch drives and they work perfectly. You just need to jumper the 651 for mini drives rather than normal so that the data separator works properly. 

On May 30, 2020, at 1:16 PM, Jeff Truck <jeff.truck@...> wrote:

Has anyone out there been able to get a '651 style microboard to work successfully with a SONY 3.5 drive?   I've attempted to recreate the '651 board.   For the most part, it works.   Small little code fragments which interact with the drive, such as Sense Drive Status, Obtain Version of the UPD765 FDC, Read Main Status, Read Result Registers, etc.   The one thing I can't get to work is a Format Track operation.  I've got a small army of probes hooked up to various logic lines and the hunt continues as to what the culprit might be, but I thought to ask the crew here to find out if someone has already gone down this path and discovered something about the newer drives or perhaps it's the fact that the 1802 is running at 4MHz - who knows.

Result Status 01 comes back with OVERRUN set which implies that the DMA request to obtain from the main system a list of C, H, R and N values is not being serviced.   I've tried to ensure that the proper DMA channel set up and number of DMA blocks is set up appropriately.   I'm still digging away at this.

You will find a picture of the new board in my photo album.
 
Jeff


taf123
 

Hi Jeff -

Congrats on finding the problem.

All of those potentially shared signal lines, !EFx, !DMA-IN/-OUT, !INTERRUPT, !WAIT, and !CLEAR, should be driven by open drain devices, such as the 74HC07 or 40107




Or isolated with diodes



With pull up resistors back at the 1802



I also like the RCA method of using the two-level I/O expansion to also expand the use of the !EFx lines, as seen in the '651 FDC board



I wish I had started with that as I'm now trying to retrofit it on the earlier ELF-ish expansion boards.

Anyways, great to hear its moving forward.  Looking forward to hearing how you get on with MicroDOS

Todd


Jeff Truck
 

Todd,

Regarding the SONY MPF920 drive - can you recall what values you used for a double-sided double density disk?   I'm specifically interested in the GAP3 parameters for FORMAT and RD/WR operations.  I'm using h54 and h1B respectively.    I've got the logic analyzer hooked up and what I am seeing does yield some promise.  I am able to run through a complete format operation but when I attempt to read a single sector I am getting Missing Address Mark errors as reported in bit 0 - SR1.   Things are looking much better then the last time I checked in.  If I alter the number of sectors per track - I started with 9 for 512 byte sectors and bumped it up to 15 I definitely see the read pattern change on RD-P signal.  In fact when I am reading track 7, head 0, sector 7 I can see 512 pulses in what appears to be a sector, but I'm still getting that nasty MA error.   Thanks!


taf123
 

Hi Jeff -

I didn't write me own software for this stuff, I just used UT71 and MicroDOS.  This assumed it was using that original Sony drive, single-sided with 70 tracks of 9 sectors.  The key difference is that the MPF920 is a 300rpm instead of a 600rpm, so as cellarcat mentioned, you need to set the jumper for "mini" floppy to get the correct transfer clock rates and correct functioning of the data separator.

This worked fine, but I did notice some noises from the drives during operations due to UT71 being set up for the old Sony drive's step rate.  I modified this and re-assembled UT71 and the noises went away.

All of the UT71 disk constants are in the source.  Here's from my version, including the changes for the more modern, but "mini", drives:

;DISK DATA CONSTANTS

BC      .EQ 04H                  ;BYTE COUNT
N       .EQ 02H          ;N
EOT     .EQ 09H          ;EOT
GPL3    .EQ 1BH          ;GPLB
DTL     .EQ 0FFH          ;DTL
FM      .EQ 40H          ;DENSITY
; ADJUSTED FOR MINI-FLOPPY MODE AND "MODERN" DRIVES - TAF
;SRT     .EQ 10H          ;STEP RATE: 15 MS
;HLT     .EQ 3CH          ;HEAD LOAD TIME1 60 MS
;HUT     .EQ 0FH          ;HEAD UNLOAD TIME: 240 MS
SRT     .EQ 0E0H          ;STEP RATE: 3 (4) MS
HLT     .EQ 08H          ;HEAD LOAD TIME1 15 (16) MS
HUT     .EQ 07H          ;HEAD UNLOAD TIME: 240 MS
DMA     .EQ 00H          ;DMA OPERATION
DMANOP  .EQ 00H          ;NO DMA OPERATION
CRCREAD .EQ 01H          ;CRC READ
DMAO    .EQ 02H          ;DISK WRITE
DMAI    .EQ 03H          ;DISK READ-
RCA     .EQ 01H          ;GROUP SELECT 1
NEC     .EQ 08H          ;GROUP SELECT 8
MAXTRK  .EQ 70              ;NUMBER OF TRACKS ON SONY
MAXSEC  .EQ 09              ;9 SECTORS / TRACK


Hope that helps,
Todd


Stuart Remphrey
 

On Sun, Jun 14, 2020 at 06:57 AM, taf123 wrote:
;HUT     .EQ 0FH          ;HEAD UNLOAD TIME: 240 MS
...
HUT     .EQ 07H          ;HEAD UNLOAD TIME: 240 MS
Just a quick note: Assuming the original comment is correct at "240 MS" your adjusted comment should be "105 MS" or thereabouts.

Rgds, Stuart "Don't have any COSMAC FDC or floppy drives at the moment, but following the discussion with great interest" Remphrey


cellarcat
 

Just to confirm I did the same as Todd and changed the step rate and head load/unload times. One interesting point is that although the Sony drives were set up for 70 tracks the format program will let you format 80 tracks. 

On Jun 14, 2020, at 8:57 AM, taf123 <todd.ferguson@...> wrote:

Hi Jeff -

I didn't write me own software for this stuff, I just used UT71 and MicroDOS.  This assumed it was using that original Sony drive, single-sided with 70 tracks of 9 sectors.  The key difference is that the MPF920 is a 300rpm instead of a 600rpm, so as cellarcat mentioned, you need to set the jumper for "mini" floppy to get the correct transfer clock rates and correct functioning of the data separator.

This worked fine, but I did notice some noises from the drives during operations due to UT71 being set up for the old Sony drive's step rate.  I modified this and re-assembled UT71 and the noises went away.

All of the UT71 disk constants are in the source.  Here's from my version, including the changes for the more modern, but "mini", drives:

;DISK DATA CONSTANTS

BC      .EQ 04H                  ;BYTE COUNT
N       .EQ 02H          ;N
EOT     .EQ 09H          ;EOT
GPL3    .EQ 1BH          ;GPLB
DTL     .EQ 0FFH          ;DTL
FM      .EQ 40H          ;DENSITY
; ADJUSTED FOR MINI-FLOPPY MODE AND "MODERN" DRIVES - TAF
;SRT     .EQ 10H          ;STEP RATE: 15 MS
;HLT     .EQ 3CH          ;HEAD LOAD TIME1 60 MS
;HUT     .EQ 0FH          ;HEAD UNLOAD TIME: 240 MS
SRT     .EQ 0E0H          ;STEP RATE: 3 (4) MS
HLT     .EQ 08H          ;HEAD LOAD TIME1 15 (16) MS
HUT     .EQ 07H          ;HEAD UNLOAD TIME: 240 MS
DMA     .EQ 00H          ;DMA OPERATION
DMANOP  .EQ 00H          ;NO DMA OPERATION
CRCREAD .EQ 01H          ;CRC READ
DMAO    .EQ 02H          ;DISK WRITE
DMAI    .EQ 03H          ;DISK READ-
RCA     .EQ 01H          ;GROUP SELECT 1
NEC     .EQ 08H          ;GROUP SELECT 8
MAXTRK  .EQ 70              ;NUMBER OF TRACKS ON SONY
MAXSEC  .EQ 09              ;9 SECTORS / TRACK


Hope that helps,
Todd


David Schultz
 

On 6/13/20 5:30 PM, Jeff Truck wrote:
I am able to run through a complete
format operation but when I attempt to read a single sector I am getting
Missing Address Mark errors as reported in bit 0 - SR1. 
Most of what I know (Well, knew. Things fade.) I learned from the data
sheet for the Western Digital 2793 FDC. In particular it has a nice
diagram of the track format that might help you here.

Google ought to be able to turn up a copy.



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taf123
 

Hi Stuart -

From the manual, here's the calculations for the three drive constant values used for Specify.

SRT occupies the upper 4-bits of the SRT/HUT byte, with a range from 1 - 16ms, with 1ms increment, but counting backwards; F=1ms, E=2ms, etc.
RCA SRT of 10H = 15ms.

HUT occupies the lower 4-bits, with a range of 16ms to 240ms, in 16ms increments.
RCA HUT of  0FH = 240ms

HLT is the upper 7-bits of the HLT/ND byte, with a range of 2 to 254ms in 2ms increments
RCA HLT of 3CH = 60ms  (3CH RSH = 1EH = 30.  30 * 2 = 60 ;-) )

In the text for Specify, it goes on to add:

"The time intervals mentioned above are a direct function of the clock (CLK on pin 19), Times indicated above
are for an 8 MHz clock, if the clock was reduced to 4 MHz (mini-floppy application) then all time intervals are
increased by a factor of 2."

The MPF920 has an SRT of 3ms, but is in mini mode, so we only have 2ms increments.  That's why I used E0H, for a value of 4ms.

I wanted and HLT of 15ms, but had to go with the nearest increment of 4ms in mini mode, so I used 08H

08H RSH = 4H. 4 * 4ms = 16ms.

And HUT ends up with a 32ms increment.  7 * 32ms = 224ms, but 8 * 32ms = 256ms, so I went with 7 but didn't adjust the comment like I did for the other two values (oops).

Best regards,
Todd


taf123
 

Hi again -

There's a good application note for the uPD765, uPD765_App_Note_Mar79.pdf, located on bitsavers.  The last page has a diagram of the track format for the then two IBM formats.

Plus it has a bunch of other good info, including a complete FDC with a simple Floppy side interface, compared to the RCA '651, which was the basis of my FDC board's Floppy side interface.

As well as a good discussion of data separators, both using an analogue PLL version (which is simpler than RCA's) and a digital version.

Cheers,
Todd


ajparent1/kb1gmx <kb1gmx@...>
 

Advice from someone that was part of the team at NEC.

Careful of reading the design notes as it was at that time 8080/Z80/8086 design
centric.  Most other CPUs had different support parts or very different bus timings.
An example is the 8257 programale DMA controller.  The 1802 has DMA but it is
not programmable other than starting address.

Do not use the analog PLL data separator, most users had great difficulty
duplicating it on a two sided board with any reliability.  It was an old design
that was not shown to be that good.  There was a follow up ap note on that but
never got noticed.

The digital (counter based) data separator in the ap-note is better and proved to
be more reproducible.

There is also a third design that was published usign PROM and Latch called DPLL
and it was by far the best and later designs incorperated that into their internal logic
(9219, 9229, and later devices).  I have a copy in my files of the note.

All of the floppy system I'd built used the latter DPLL as it was easy, reliable and
low parts count.

Allison
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Jeff Truck
 

Allison,

Would you kindly share any material you have on this DPLL approach?

Thanks!
Jeff

On Mon, Jun 15, 2020 at 3:32 PM ajparent1/kb1gmx <kb1gmx@...> wrote:
Advice from someone that was part of the team at NEC.

Careful of reading the design notes as it was at that time 8080/Z80/8086 design
centric.  Most other CPUs had different support parts or very different bus timings.
An example is the 8257 programale DMA controller.  The 1802 has DMA but it is
not programmable other than starting address.

Do not use the analog PLL data separator, most users had great difficulty
duplicating it on a two sided board with any reliability.  It was an old design
that was not shown to be that good.  There was a follow up ap note on that but
never got noticed.

The digital (counter based) data separator in the ap-note is better and proved to
be more reproducible.

There is also a third design that was published usign PROM and Latch called DPLL
and it was by far the best and later designs incorperated that into their internal logic
(9219, 9229, and later devices).  I have a copy in my files of the note.

All of the floppy system I'd built used the latter DPLL as it was easy, reliable and
low parts count.

Allison
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