Boot Circuit - Correction #memory


An error in the previous post was brought to mi attention by another user. -Thanks again!

 This is the memory circuit in my system. It is added onto a Super Elf. View the drawing in MS Paint
or Photo Viewer.

 The NAND flip-flop and OR gate allow to use the M key select whether the Monitor or an application
loaded at 0000 runs when the Go key is pressed, as in the original Super Elf design.

 The flip-flop is set by the M (Monitor) key. It's cleared by the /R (Reset) key or, thru the NAND gates,
by either of the /P=Q outputs of the HC688's, when an EEPROM is selected (EE1 or -2 /CE). The HC688's are wired
in the Mike McLaren ROM addressing circuit. When the user starts the system by keying R, M, G the flip-flop
is set and the OR gate holds /RDENA High so the CPU reads FF on every fetch. This makes the address bus increment. When either of the HC688's /P=Q
lines goes Low the flip-flop clears, reads are enabled, and the ROM code runs.

 When the user keys R, G reads are enabled and execution begins at 0000.
Since this is controlled by the EEPROM selects, either EEPROM at any address can be used for a Monitor.
 The two EEPROM circuits allow selecting which monitor to use, and in-system rewriting of the EEPROMs.

 One quirk: If you do a Reset, Monitor while the EEPROM code is running the flip-flop won't set.
Just hold the Monitor button, hit Go and release Monitor.

 For non-Super Elf designs the /R key line could go to CPU /CLR and M key could be a pushbutton switch
to +5V with a pulldown resistor.

 I have found this design to be reliable and VERY useful. The design was inspired by an article