Topics

Todd's ELF-ish gets some more more I/O #ELF #Homebrew

taf123
 

Hi 1800 fans -

This week, I finished adding the CDP1851 Programmable I/O Interface and the CDP1878 Dual Counter-Timer to the VIS board.  These have nothing to do with the Video Interface System, but there happened to be enough space for them on that board.

Both of these I put in I/O-mapped space.  Since each uses multiple N-line decodes, I used a dedicated I/O level for each, IO2 and IO3, respectively. These are used as CS and also control a 4016 to allow them access to the N-lines, as was done with the CDP1869 VIS.  If any of the N-lines are asserted while the 4016 is enabled, the CDP1857 I/O bus buffer shared with the VIS is activated.





The CDP1851 uses 2 of the N-lines together with the I/O level as CS.  Either Port A or Port B can generate an interrupt.  I tied them together and use a jumper to select either interrupt or !EFx polling.  Reading of the status register can determine which port issued the interrupt.

I present each port to a separate connector.  Since the default mode is input, I tied all of the lines to pull-up resistors.


The CDP1878 decodes all three N-lines, and I use the I/O level as CS.  The chip can generate an interrupt when either timer/counter expires, and again I use a jumper to select between interrupt and !EFx polling operation.

Each timer can use a separate clock input.  For Timer A, I use the CLK_OUT line from the CDP1879 Real-Time Clock, which can be programmed for one of 15 periods related to real-time.  For Timer B, I added a dedicated 1Mhz oscillator to allow it to time shorter duration events. (this is the maximum clock input frequency for the CDP1878).

Each clock can be controlled by an external gating signal or controlled by software.  Also, each timer can generate an output, and an inverted output.  These I bring to a 10-pin connector, together with the RTC CLK_OUT signal.



Here's they are all wired up.



The I/O pins on the CDP1851 are on the wrong side of the chip considering where I have the port connectors, so I mounted it upside down compared to the other chips.
It does mean that Port B is the top port, instead of Port A as one would normally want. But, it made wiring a lot easier, so there


And top view.  The VIS board is now completely populated.



Ready for testing - I'm going to have to get a bigger house soon...



For testing the CDP1851 Programmable I/O, I used the same test bed as I previously used for the Byte I/O CDP1852 ports on the expansion chassis.  Since the CDP1851 is programmable, I set Port B to be input and Port A to be output, to support the same test.  I just had to modify the code to properly initialize the CDP1851 and to use the correct two-level I/O codes to access these ports.

This pictures shows that the test was successful. You'll have to take my word for it that I had just pressed the 9 button.



Or, you can watch the exciting video, attached.

Of course the CDP1851 supports more complicated configurations, but tests for those will have to wait.

For testing the CDP1878 Dual-Timer, I modified the above test by adding a 10 second delay between when the button is pressed and when the display is updated. Instead of using a delay loop, this is using the Timer A from the CDP1878 Dual 16-bit timer. In this demo, Timer A is driven by the programmable clock out from the CDP1879 Real-Time Clock, which I've set for a period on 500ms.

My not very scientific timing showed the delay was not quite 10 seconds, so I have some further investigations. But this test verified to basic functionality.

Video also attached.