Hi All -
I ran across a set of HM6167LP-8 16k x 1-bit SRAMs on eBay and decided I'd give the ELF-ish another 16k of SRAM.
The HM6167's are CMOS versions of the Intel 2167 NMOS chips.
For address decoding, I've decided to use a CDP1866 to decode the 64k address space into four 16k blocks, and then just use the second one, so this addition fits above the existing 16k and below the EPROM starting at 8000.
The CDP1866 will also latch two of the required high addresses lines. For the remaining four, I'll use a 74HC75 Quad bistable transparent latch.
However, I am concerned about what the data sheet for the 2167/HM6167 says for the read cycle:
"Addresses valid prior to or coincident with !CS transition low".
Even though the CDP1866 will gate the !CS with the !MRD, the !MRD on the CDP1802 gets asserted *before* the low address byte is valid. For the other memories I've used with the ELF-ish, this hasn't been a problem, but it was a problem for the AM9511 APU I memory mapped, which required me to delay the !CS line.
Does anyone have any experience with these memory chips? From the timing diagram, it doesn't look like they latch the address bus on !CS as it needs to be held for the duration of the cycle:
It also doesn't say this for the Write cycle.
Anyone have any thoughts or experience here? It's a lot of wire wrapping to discover that they won't work, so any guidance would be appreciated.
I've attached the data sheets as well as the complete schematic for the planned 16k board.