So, on to the VIS build. There are many options to choose from when designing a VIS. I decided I didn't want to decide and included everything:
Instead, I decided to again borrow from the ELF2k, this time using the AT89C2051 MCU based PS/2 keyboard to byte-parallel ASCII used on their GPIO board. But instead of using their PLD-based interface circuit, I decided to just go with a CDP1852 byte-I/O in input mode - the built-in CLOCK / !SR action could be used for the necessary hand-shaking.
The VIS data sheet requires the use of one pair of CDP1856 bus buffers/separators between the pmem and the CPU data bus. But since I am using buffering for memory-mapped I/O and I/O-mapped I/O as well, I'll have to include additional buffers of both types. Plus, I need to interface to the two-level I/O system.
Phew - better get to it.
Similar to the 12k memory expansion board, I used two 74HC244 octal buffers for the address bus and signals. Additionally, I used another 74HC07 HEX open drain buffer for the !EFx and !IRx lines.
I decided to use I/O level IO1 (where the latched bit 1 is set) for the VIS. Since the CDP1869 decodes the N-lines itself, I use a 4016 quad bilateral switch, controlled by the IO1 line, to limit its access to the N-lines, with pull-down resistors to present 000 when a different I/O level is latched.
Since I planned on doing this a few more times, I went ahead and wired up a few of these lines to the CDP1875 used as a latch back on the expansion chassis.
The IO1 went to the 4016 control lines.
I'll just show here the combined N-line 4016, CDP1869, the two CDM6116 2k x 8-bit pmem and cmem SRAMs, and the CDP1856 pair acting as bus separators for the pmem.
The CDP1876 connects to the cmem bus, the "internal" CDP1869 to CP1876 lines, and the PCB.
The CDP1876 has two requirements for its data bus connection - it presents the cmem access as memory-mapped I/O, but also presents its control register as I/O-mapped I/O, using the CDP1869 decoded !N=3 line.
For my bidirectional buffering, this requires both a pair of CDP1857's, for I/O-mapped use, and a 74HC245 bidirectional buffer for the memory-mapped use. I could have used another pair of CDP1856's instead, but I was running low and the pair takes up more board space.
Finally, the CDM6264 8k x 8-bit memory is wired in to both the PMA and CMA lines, for addressing, and the cmem bus.
Here's what all of that looks like:
The CDP1857's will also be used to buffer I/O-mapped devices in I/O level's 2 & 3, later, so that combined IO23_EN line is diode/resistor OR-ed with the N=3 line for a combined VIO_EN (VIS I/O ENable) line.
Finally, the DOT clock. The data sheet calls for a 5.67Mhz crystal for NTSC use - but I can't find one. If anyone knows where to source one, please let me know.
Since I couldn't find the required crystal, I looked around for alternates, which could get close enough. I found some crystals and oscillators which, when /2 or /4, would get close.
So I wired in for all three options. For the separate crystal controlled oscillator, I copied the 74HC04 based oscillator I used with the RTC, since a 74HC04 is fast enough for this.
Then for the division, I used both halves of a 74HC74, with jumpers to select between /2 or /4.
I figured between all of this, I should be able to find a good enough clock.
ICAN-6953 includes a full assembly listing of a VIS demo program which uses the UT4 sub-routines for character input, so I could start building at this point and come back to the PS/2 keyboard interface once all of this was working.
I started with an 11.2896Mhz oscillator: /2 = 5.6448Mhz, which is close to the specified 5.67Mhz.
It's nice when a plan works out.