Airspy architecture

Alberto I2PHD

A few naive questions, originated from my attempt to understand the architecture of the Airspy.

The tuner is an R820T2, which converts in the analog domain down to a low IF, just above 4 MHz.

First question : from the simplified block diagram of that chip, it doesn't seem to use a quadrature
mixer. That notwithstanding, the image rejection reported from its data sheet is 65 dBc... how is
that possible ?

A more detailed look shows that it has two IF outputs, pin 12 and pin 13, marked as IF N and IF P.
In the unconfirmed hypothesis that those outputs are actually I and Q, in other words the mixer
is as a matter of facts a quadrature mixer, then those two outputs must be digitized by the
12-bit, 80 MHz high speed ADC of the NXP LPC-4370 processor, which is a single ADC.
So it should work in a time interleaved fashion... is this correct ?

A bit of light on the Airspy architecture would be welcome, thanks.

73 Alberto I2PHD
Credo Ut Intelligam

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