My personal recollection: The SOS processor based on the HP 3000 architecture was specifically developed for Amigo (HP 300). The desk-sized HP 300 required a chip implementation of the HP 3000 process

That disassembly on Marc's video is the only one I am aware of. CurciousMarc showed a listing on screen and I am certain that is a full disassembly. We used to keep those listings on greenbar paper in

CuriousMarc has a set of YouTube videos on the topic. --Steve

Hi Dave. I know the gold recycling is going on everywhere. It's the story about building s 2109 from two other machines I was referring to. --Steve

Jack, you are the least lonely English lit major I know. --Steve

Thanks for the story of your 2109 FrankenMini, Achim. So gold plating on printed circuit boards is the equivalent of acid-free paper for printmaking or bookmaking. Only in this group, I think, would y

Hi Lee, I certainly would never assert that <all> HP engineers did things squarely according to Hoyle (or Bill and Dave). I've got stories too. Particularly software stories where OS software was terr

Hi Anders, I must respectfully disagree with your characterization a bit. Yes, HP charged high prices (we joked that HP stood for "high performance" and "high prices"), but in the 1960s, 1970s, and 19

I wasn't planning to reply to this thread, but if you're planning on using that explanation for ARM's journey in an architecture class, please take a look at this article, which I wrote a couple of ye

"My locked designs" should have been "My clocked designs". --Steve

Hi Achim, DRAMs from different vendors <may> need different delay lines to operate at maximum performance, but a good designer (and HP had lots of those) designed a memory controller and array to acco

Almost forgot: Delay line memories, the mercury ones in the original 1940s computers and the magnetostrictive ones used in the old calculators, were acoustic. This is something I did not understand fo

Yes Achim, it's really a delay line - a loooooong piece of wire, wound on a core. Back then, before DRAMs were synchronous and clocked, there were two ways to generate the required RAS/CAS timing. One

Not that I'm capable of this level of design (any more), but scoping the problem you'd need a little logic and 256 kbits of RAM to emulate the M register and the maxed-out HP 9830B 30,144 byte memory.

I vaguely recall using the RTS/CTS handshake pair when working with the 2600 terminals to control the data flow at 9600 baud while I was developing the HP 98036A serial interface and the System Progra

Martin, Thanks for capturing that history! --Steve

#HP9000S300

Thanks Jack, It seems that SemiWiki took their copy down. Not sure why. --Steve

The HP Nanoprocessor was instrumental in the design of the HP 98034A and 98035A I/O cards. I played a truly small role in helping to debug the 98034A, which was designed by Dick Barney. It was designe

That was already done. Take a look at the subject line. --Steve

In theory there is no difference between theory and practice. In practice there is. Yogi Berra