Re: 9825 restoration notes and questions


On Jan 30, 2017, at 7:16 PM, Jack Rubin <j@...> wrote:

If the Monitor Bus connection is intact, I think I should find D2MapClk on pin 6 of U43 and DMapClk on pin 15 of the same chip. Does that make sense? Should the clocks should be 6MHz? 

I suspect that what Tony has labeled as DMapClk and D2MapClk may actually be the internal state signals from the BPC that indicate what type of memory access is being performed, and will not be periodic 6 MHz clocks, but dependent on what instructions are being executed at any point in time.

My logic programmer won’t read a 2332 ROM (i.e. U29), but I could rig up my 16500C or an ATMega to get the contents for comparison.

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