Sonnet via fence or array


Neil Smith G4DBN
 

Any Sonnet software users out there? I am modelling a grounded coplanar waveguide and need to create a load of grounding vias either side of a PCB conductor, but I can't find a way to create a line or rectangular block of vias other than by cut and paste. I'm using Sonnet Lite 15.53. I want to test the effect of via size and spacing, so ideally I'd like to parameterize those characteristics.

I've deliberately adjusted the CPW track width to cause a mismatch in this simulation. Grey plane is ground and this is modelled on RO4350 at 8 to 15 GHz.

Now I want to have parameter settings for via diameter, via spacing, distance of via from edge of the GCPW ground, track width and CPW gap. Model is still under 20 MB so still manageable. Does anyone have suggestions of good help resources for Sonnet Lite?

Neil G4DBN

(if replying to the group, please delete the images in your reply to save space)


Murray Niman
 

Hi Neil

Unfortunately Sonnet doesnt have the rather nice muliple-copy command and object linking that 3d editors/tools often have

instead create a set of identical vias and then you need to parameterize their position/spacing (or distance from a common anchor point) in a similar way to the combline filter example using the Tools 'dimension parameter' feature

The

73

 Murray


Neil Smith G4DBN
 

Thanks Murray, I'll see how it goes. The number of vias is limited because of the 32 MB memory limitation in Lite, but the lines I am modelling are very short. By the time I have around 20 vias each side of the CPWG, I'm pretty much at the limit, and I still need to model the transition to a connector, so perhaps 16 per side will be my limit.

I would really like to have solder resist over the CPW, but I can't imagine the low-cost fabs will give me a choice of resist with dielectric properties suitable for leaving the tracks as bare copper at 10 GHz. I really want to keep the track temperature down so I don't end up with the track delaminating from the substrate and turning to plasma after a few thousand heat cycles as I call CQ fruitlessly into the void (well, at the moon).

Neil G4DBN

On 12/05/2021 20:35, Murray Niman wrote:
Hi Neil

Unfortunately Sonnet doesnt have the rather nice muliple-copy command and object linking that 3d editors/tools often have

instead create a set of identical vias and then you need to parameterize their position/spacing (or distance from a common anchor point) in a similar way to the combline filter example using the Tools 'dimension parameter' feature


Murray Niman
 

hi Neil
To save memory
vias can be coarser polygons such as hexagons or even squares
spacing gaps can be eighth-wave

fields and currents in CPW edges/gaps are really intense so avoid any uncertain resists or coatings there

if you have an option that is etchable for your cpw gaps, try the 1oz copper rather than .5. As that will be far better at heat transport

73. 

     Murray


Neil Smith G4DBN
 

So far, the losses even in 4350 look to be less than 0.08 dB per 6 mm, and at 40W out, that's less than a watt - but in a small area. About half is dielectric loss and half is copper loss. I can't model rough surfaces or trapezoidal edges from etching in Lite, but so far, this looks pretty much as expected.  The bleed through the via fence is visible, but it is way down.  I have a rather exciting resonance at around 25 GHz, and the characteristic impedance is falling gently as the frequency rises towards 15 GHz. 10.368 GHz is looking very good.

As expected, changing the via spacing doesnt have much effect once I'm at less than 1mm spacing, but I can see small leaks starting between the vias.  Of course the other issue with Lite is that vias are perfect conductors. The smallest vias model as squares anyway in a 0.1 mm cell grid.

Right, I'll see if I can get the parameterisation to work and try varying the track width/spacing of the CPW as well as the via fences and see what the thermal impact looks like.

Thanks for help.

Neil G4DBN

On 13/05/2021 00:29, Murray Niman wrote:

hi Neil
To save memory
vias can be coarser polygons such as hexagons or even squares
spacing gaps can be eighth-wave

fields and currents in CPW edges/gaps are really intense so avoid any uncertain resists or coatings there

if you have an option that is etchable for your cpw gaps, try the 1oz copper rather than .5. As that will be far better at heat transport

73.