Re: Hi Speed Comparator operation


Rien Eradus PA0JME
 

https://www.analog.com/media/en/technical-documentation/data-sheets/lt1016.pdf

Op 20-5-2021 om 15:18 schreef Rien Eradus PA0JME via groups.io:

A bit further datasheet shows

Input Impedance and Bias Current

Input bias current is measured with the output held at 1.4V. As with any simple NPN differential input stage, the LT1016 bias current will go to zero on an input that is low and double on an input that is high. If both inputs are less than 0.8V above V, both input bias currents will go to zero. If either input exceeds the positive common mode limit, input bias current will increase rapidly, approaching several milliamperes at VIN = V+.

Op 20-5-2021 om 12:04 schreef G8ZHA via groups.io:
I have built a couple of W1GHz projects: a GPS locked 10MHz osillator and a 100MHz PLL board. Each of his circuits uses a LT1116 hi speed comparator to lift the oscilator signal up to 5V CMOS logic levels to feed the dividers.

On the 100MHz PLL PCB, there is a 3.3V osc, feeding a MC12080 Div by 10 prescaler, AC coupled into the non-inverting input ofthe LT1116. The inverting input is tied directly to ground. I can see a nice square wave signal into this pin, about 1.5V pk-pk, centered on 0V. The outputs, which are open circuit, are very distorted, see photos.

I thought that this may be because the signal is outside the common range of 0 - 2.5V for the LT1116, so I biased the input to the middle of the voltage range but was not successful.

Am I missing something obvious?

I also built the 10MHz version, which feeds the osc straight into the comparator. I hadn't got a LT1116, so used a LT1016 instead, which has a common mode input range of 1.25 tp 3.75V range. Again, I biased the input signal to the middle of the voltage range, but saw the same distored oyutput.

(in the UK, the LT1116 is not available from RS etc)

I am at a loss to understand what is going wrong.

Rich G*ZHA

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