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7L5 dot frequency reset bug - any clues or a fix?

Cliff Carrie
 

The 7L5 manuals say the Dot Frequency should reset to 0.000 kHz at power on. There have been previous posts about this not happening, but no mention of a fix. I have personally seen two 7L5s, including the one I am currently using in my 7854, that reset to a varying frequency near 3778 kHz. I have forced a reset using a jumper to trigger the power-on reset timer. The Dot Frequency goes to 0.000 kHz during the reset but goes back to 3778.xxx kHz when the reset timer ends. All other modes and indicators reset as expected. I don't think this is unique to the 7854 power on since the mainframe was already powered up before I did my test. I suspect a timing race in U830 as the reset pulse turns off. I know this is a minor annoyance, but the circuitry is there, and I'd like to make it work properly. My 7L5 service manual is 070-2184-01. The reset timer is Q621 on Drawing 5 lower left. U830 is on Drawing 8 (see pins 4 and 17).

1: Has anyone experienced this on the 7L5 in a mainframe other than the 7854?
2: Who else is experiencing this in a 7854?
3: Does anyone have a fix?

Cliff Carrie

Dave Casey
 

I can test mine out tomorrow and let you know if it does the same thing.

Dave Casey

On Sat, Dec 7, 2019 at 4:46 PM Cliff Carrie <cliffcarrie@...> wrote:

The 7L5 manuals say the Dot Frequency should reset to 0.000 kHz at power
on. There have been previous posts about this not happening, but no mention
of a fix. I have personally seen two 7L5s, including the one I am currently
using in my 7854, that reset to a varying frequency near 3778 kHz. I have
forced a reset using a jumper to trigger the power-on reset timer. The Dot
Frequency goes to 0.000 kHz during the reset but goes back to 3778.xxx kHz
when the reset timer ends. All other modes and indicators reset as
expected. I don't think this is unique to the 7854 power on since the
mainframe was already powered up before I did my test. I suspect a timing
race in U830 as the reset pulse turns off. I know this is a minor
annoyance, but the circuitry is there, and I'd like to make it work
properly. My 7L5 service manual is 070-2184-01. The reset timer is Q621 on
Drawing 5 lower left. U830 is on Drawing 8 (see pins 4 and 17).

1: Has anyone experienced this on the 7L5 in a mainframe other than the
7854?
2: Who else is experiencing this in a 7854?
3: Does anyone have a fix?

Cliff Carrie



Cliff Carrie
 

At 7L5 SN B060000 Tek changed U830 from PN 155-0117-00 to 155-0198-00. This may be a reset bug fix, but I have not found any Tek info on it. Also, there is a typo in Diagram 8. U830 shows as PN 155-0177-00. The parts list (and my 7L5) show 155-0117-00.

Dave Casey
 

My late 7L5 (B09...) powers up in my 7854 at various frequencies. Also
sometimes it powers up in 10dB LOG mode and other times in LIN mode. I
powered it off and on a few times (with varying off times) and observed the
following:
1266.75KHz, LOG
2000.00KHz, LIN
3777.25KHz, LIN
3767.25KHz, LOG
3795.00KHz, LOG
Sometimes I tuned it down to zero before power cycling, sometimes I didn't.

This 7L5/7854 combo has the known readout bug, and this 7L5 has not been
modified for the 7854 CHOP mode issue.
I have another 7L5 I can dig out to test, but I would expect to see similar
results.

Dave Casey

On Sun, Dec 8, 2019 at 1:09 PM Cliff Carrie <cliffcarrie@...> wrote:

At 7L5 SN B060000 Tek changed U830 from PN 155-0117-00 to 155-0198-00.
This may be a reset bug fix, but I have not found any Tek info on it. Also,
there is a typo in Diagram 8. U830 shows as PN 155-0177-00. The parts list
(and my 7L5) show 155-0117-00.



Cliff Carrie
 

UPDATE:
The change of U830 (dot frequency counter) from PN 155-0117-00 to 155-0198-00 at 7L5 SN B060000 changes this part from a leadless ceramic carrier to a leaded (DIP) ceramic carrier. I don't know yet if the reset bug was fixed in the newer chip, Having recently acquired one of the later 155-0198-00 leaded chips, I wonder if it could be installed, temporarily for a test or permanently in the leadless carrier socket without damaging it. Pinout seems unchanged. I visualize a plastic backup block under the chip between the two rows of pins to hold them against the leadless socket contacts. I can easily create a pressure pad between the chip and the adjacent circuit board to ensure it doesn't pop out of the socket.

Has anyone ever tried this (installing a DIP leaded chip) in any leadless socket (not necessarily in a 7L5)?

I certainly don't want to replace the 40 pin socket for a test that may show no change and/or some new incompatibility.

One more note: the serial number on a 7L5 does not tell the whole story about the circuit level. Tek released at least 3 versions of a major update kit 040-0872-xx. If your 7L5 has an added front panel "B - save A" lighted pushbutton it is B070000 or higher or has this kit installed. Mine with serial B03xxxx and the 040-0872-01 kit is equivalent to at least SN B081400. Two boards (Storage and Digital Averaging) were also replaced with a single board. Note that there are other serial numbers where boards changed part numbers, but auditing my 7L5 against the manual, there don't seem to be any circuit changes or improvements not covered in the update kit.

Cliff Carrie

Dave Casey
 

Cliff -

Did you see my response from December 8? I have a late 7L5 (> B090000) that
doesn't sound like it works any better than yours with respect to the reset
behavior.

Dave Casey

On Mon, Jan 20, 2020 at 12:19 AM Cliff Carrie <cliffcarrie@...>
wrote:

UPDATE:
The change of U830 (dot frequency counter) from PN 155-0117-00 to
155-0198-00 at 7L5 SN B060000 changes this part from a leadless ceramic
carrier to a leaded (DIP) ceramic carrier. I don't know yet if the reset
bug was fixed in the newer chip, Having recently acquired one of the later
155-0198-00 leaded chips, I wonder if it could be installed, temporarily
for a test or permanently in the leadless carrier socket without damaging
it. Pinout seems unchanged. I visualize a plastic backup block under the
chip between the two rows of pins to hold them against the leadless socket
contacts. I can easily create a pressure pad between the chip and the
adjacent circuit board to ensure it doesn't pop out of the socket.

Has anyone ever tried this (installing a DIP leaded chip) in any leadless
socket (not necessarily in a 7L5)?

I certainly don't want to replace the 40 pin socket for a test that may
show no change and/or some new incompatibility.

One more note: the serial number on a 7L5 does not tell the whole story
about the circuit level. Tek released at least 3 versions of a major update
kit 040-0872-xx. If your 7L5 has an added front panel "B - save A" lighted
pushbutton it is B070000 or higher or has this kit installed. Mine with
serial B03xxxx and the 040-0872-01 kit is equivalent to at least SN
B081400. Two boards (Storage and Digital Averaging) were also replaced with
a single board. Note that there are other serial numbers where boards
changed part numbers, but auditing my 7L5 against the manual, there don't
seem to be any circuit changes or improvements not covered in the update
kit.

Cliff Carrie



Jean-Paul
 

Cliff and Dave:

On my 7L5, SN B09..., same: Random init dot, never 0, sometimes 3777.
Be fine to engineer a fix!

How many out there have the tracking gen, OPT 25, a very useful option?

Jon

Cliff Carrie
 

Thanks for the data, Dave.

I guess the only remaining question in my mind is whether the reset bug ever shows up with a 7L5 in NON-7854 mainframes.

Now I have to start chasing the two apparent design errors more in-depth. My 7L5 is now in bug-free condition except for the "reset" and "below 10KHz display" errors. I have two extender cables. Time to do some serious debugging.

Cliff Carrie

Dave Casey
 

I can try one in a 7603 at some point in the not too distant future.

Dave Casey

On Fri, Jan 24, 2020 at 10:55 PM Cliff Carrie <cliffcarrie@...>
wrote:

Thanks for the data, Dave.

I guess the only remaining question in my mind is whether the reset bug
ever shows up with a 7L5 in NON-7854 mainframes.

Now I have to start chasing the two apparent design errors more in-depth.
My 7L5 is now in bug-free condition except for the "reset" and "below 10KHz
display" errors. I have two extender cables. Time to do some serious
debugging.

Cliff Carrie



Dan G
 

I also experience this failure-to-reset problem on my 7L5 (B09xxxx) when installed in the
7854 mainframe. However, the problem never appears when the 7L5 is installed in the
7603 or the R7603.

And now for something interesting: if I turn off the 7854, and then turn it back on
four seconds later, the 7L5 resets itself properly. But if I wait 8 seconds instead of 4,
the reset bug appears again. This is quite reproducible with my hardware.
I wonder if it is related to the R621/C621 RC constant...


dan

Cliff Carrie
 

Does anyone have a datasheet for 7L5 U830 on Diagram 8 (PN 156-0117-00)?
I have always suspected a timing race of some sort between the sequence and rate of turn-on of the 7854 power supplies and the power-on reset pulse. Another interesting thing is that the "reset" pin (4) on U830 is actually labeled "LOAD". I have accounted for 39 of the 40 pins on this IC and none of them appear to be inputs for a data load operation. Pin 27 does not appear in the diagram. Checking if any printed wiring connects to it requires a major teardown of the 7L5, so I have not done this yet. The only other apparent input is SERIAL IN (Pin 17), but it is pulled low by the reset net. There are a couple of other possible candidates, but they are fed only from option connectors that are open on my 7L5. So how does U830 get told to go to zero (and get it wrong)? I have run one test in my 7854, triggering the full reset net with a jumper after the scope is fully powered up. The dot frequency goes to zero while the reset is asserted, but then shows the usual wrong result after, around 3778 kHz. That would seem to eliminate any power supply turn-on issues. Next time I tackle this bug, I will connect a jumper to the reset net and pulse it with different durations to see if the bug changes. I suspect U830 resets to zero and then counts up clock pulses until the reset pulse ends. That might allow an opportunity for differences between mainframes to have unintended consequences. It might also explain the puzzling name LOAD for Pin 4. Strangely, under 156-0117-00 the Tek Common Design semiconductor manual pages 4-5 and 4-6 reference the industry standard 74161 presettable counter (a 16 pin chip with parallel loading; U830 has 40 pins). Maybe U830 has two dies in it, the 74161 and a custom chip.
A datasheet for U830 (ideally with a functional description) sure would be useful at this point.

Regards, Cliff Carrie
________________________________
From: TekScopes@groups.io <TekScopes@groups.io> on behalf of Dan G <dgajanovic@...>
Sent: Thursday, February 27, 2020 2:08 AM
To: TekScopes@groups.io <TekScopes@groups.io>
Subject: Re: [TekScopes] 7L5 dot frequency reset bug - any clues or a fix?

I also experience this failure-to-reset problem on my 7L5 (B09xxxx) when installed in the
7854 mainframe. However, the problem never appears when the 7L5 is installed in the
7603 or the R7603.

And now for something interesting: if I turn off the 7854, and then turn it back on
four seconds later, the 7L5 resets itself properly. But if I wait 8 seconds instead of 4,
the reset bug appears again. This is quite reproducible with my hardware.
I wonder if it is related to the R621/C621 RC constant...


dan

Dan G
 

According to my service manual, U830 is p/n 155-0117-00 for s/n below B060000,
and p/n 155-0198-00 thereafter. Notice that these are 155- not 156-.

155-0198-00 is mentioned on page 3-6 of the semiconductor manual, but there is
no information beyond a general description of "knob readout counter".

Based on the 7L5 schematics and the labeling of the U830 pins, the reset logic
pulls down both _LOAD and N SERIAL IN lines simultaneously, which should load
zeros into the register. However, for this to have any effect, I would expect that a
sufficient number of clock pulses (17 at least, to zero out a 17-bit BCD frequency
register) must come in on the SERIAL CLK line while the _LOAD line is held low.

The serial clock is provided by the mainframe's TS1 line (time slot 1).

In my 7603 mainframes, the SERIAL CLK line is at ~5V, pulled down to ~4.0V
by the TS1 pulses. This level seems enough to trigger the U830 serial clock input.

In my 7854 mainframe, however, the SERIAL CLK line is only pulled down to 4.2V.
This does not seem enough to trigger the U830 shift load logic, and explains why
forcing a reset after power-on still fails to reset the frequency register.

If I add a 680 Ohm resistor in parallel with R843, then the SERIAL CLK line is
pulled down a little more to 4.1V, which seems enough to trigger U830.
And, voila! The 7L5 now resets itself properly on power-on. Forced
resets (by carefully discharging C621) also take hold.

**IMPORTANT**: I am in no way suggesting at this stage that anyone modify
their instrument this way as an actual "fix". 7L5s now seem few and far
between, and I would be mortified to learn that this post had inadvertently
resulted in a reduction of the number of remaining undamaged units...

I hope to have some time in the near future to dig a little deeper, and identify
the root cause of this reset issue. In the meantime, by narrowing down the
area of interest, perhaps the information presented here might help others
do the same.


dan

Nenad Filipovic
 

Hi Dan,

Excellent analysis. I'm puzzled by the design of the level shifter
consisting of R841, C841, VR840 and R839. Assuming both SERIAL CLK and TS1
inputs have internal pull-ups to 5V, then mainframe TS1 pulses should be
able to pull SERIAL CLK much lower than 4V in steady state operation. Did
you make your measurement exactly at turn-on, thus recording the true
transient response? R841-C841 time constant is 1.38s, therefore this level
shifter would fail if not given enough time for C841 to charge. This would
also explain your observation that 7L5 resets properly if you wait only 4s
after powering down your 7854.

Best Regards,
Nenad

Dan G
 

I suspect that the design goal of the SERIAL CLK level shifter is to provide dual
access to U830's serial load inputs: initially by the reset logic in the first few
seconds of operation, and thereafter exclusively by the option interface via J3020.
This would allow an external controller to directly drive U830 pins 4, 17 and 37,
and thus set the dot frequency to any value. (I would not be surprised if
Tektronix used test fixtures that could do this during instrument calibration:
adjusting the A Oscillator Memory Gain requires the dot frequency to be
changed repeatedly between 0 kHz and 4999.75 kHz. Using the dial to do this
manually gets tedious really, really quickly.)

A general description of how U830 reset works is given on page 2-14 of the
service manual, but I did not see any mention of how option access arbitration
is accomplished.

I've reassembled my 7L5 last night, so the following is from my (imperfect) memory:

The TS1 pulses have a period of ~2 ms and are ~50 us wide.

Looking at the VR840 anode, the TS1 signal comes in at 0V, with the pulses pulling
down to -15V. U830 pin 21 input seems to have an internal pull-up resistor and a
reverse clamping diode. Combined with VR840 and R839, they act as a DC-coupled
level shifter to convert the TS1 pulses into something that is TTL-compatible.
So, this is fairly standard fare.

The AC-coupled level shifter for the SERIAL CLK input is more interesting.
The amplitude of the TS1 signal at the VR840 cathode is ~14V p-p (the zener
reverse breakdown voltage is somewaht higher than the U830 pull-up voltage).
When C841 just begins to charge, the TS1 pulses will dip well below 0V, resulting
in pulses near 0V at U830-37. So far, so good. But as C841 charges, the DC level
starts to rise, raising the pulse levels with it. When steady state is reached (i.e. C841
is fully charged), the TS1 signal at the cathode of CR843 rests at 16V, pulled down to
somewhere between 2.5V and 3.5V by the pulses (I can't remember the exact value,
and it depended on the mainframe). The forward drop across CR843 and a small
drop across R843 result in the 4V to 4.2V levels at pin 37 that I had reported in my
last post.

I've done a few more quick measurements that did not required a full disassembly
of the unit:

_LOAD and N SERIAL IN are pulled down for ~2 seconds from when AC power
is applied. So, U830 must load the 17 zero-bits within this period.

In the 7603, TS1 pulses are available practically as soon as AC power is applied --
definitely within the first 100 ms. The +5V supply has also stabilized by this point.
I can observe SERIAL CLK pulses at U830-37 start off at full amplitude (i.e. going
from ~5V down to 0V), and rising up to steady-state 5V->4V within a second
of AC power being applied. This is the sliding level shift circuit in action.
By this point, U830 should be fully reset.

In the 7854, however, TS1 pulses only come online approximately 1 second
after AC power is applied. By this time, C841 is close to fully charged, and
SERIAL CLK pulses, when they finally show up, are already near their steady
state 5V->4.2V levels.

The quick hack that I described in my previous post (decreasing the value of
R843) effectively disables the sliding level shifter and causes TS1 to have
permanent control of SERIAL CLK. A more reasonable modification might be to
increase the C841/R841 RC constant somewhat to account for TS1 pulses
not being available immediately on the 7854.

A 50% increase in value of either C841 or R841 might do the trick, and still
perform correctly in non-7854 mainframes. I will give this a try the next time
I open up my 7L5.



dan

Dan G
 

The 7L5 Log Sweep option (option 21 and supersets) uses the U830 serial
load interface to set specific dot frequencies during its log sweep.
It uses its own clock, derived from a local oscillator, so it seems very important
that the C841/R841 sliding level shifter get out of the way, as it were,
once the reset is complete. Otherwise, the TS1 pulses would interfere with
option 21's load clock, and cause data corruption during the serial transfer.


dan