Topics

Purpose of Q32 in S-52


Albert Otten
 

Hi all,

A recent topic (ending at message #168946) about S-52 repair brought up the mysterious role of Q32. During normal S-52 operation Q32 will never conduct .
Anyone an idea? Some kind of protection perhaps, but against which condition?

Albert


unclebanjoman
 

Against excessive positive (+15 V) supply I presume.
If for any reason the positive suplly voltage is too high, the TD can be damaged by an excessive current.
It is veeery small and must tolerate 50 mA peak....
Doing so, with Q32 conducting the TD never fires. A some kind of minimal security.

Max


 

On Tue, Jul 7, 2020 at 04:07 PM, Albert Otten wrote:


Anyone an idea? Some kind of protection perhaps, but against which condition?
Just a hunch, didn't study the schematic much nor thought this through but low -12V (closer to 0V) would lead to Q32 conducting from ca. -7.5V (?), pulling down on R30 (point 10). Could this stop the TD from permanently being in the triggered state (carrying I > Ip) with risk of being damaged? The other negative supply voltages will remain present to say at least -6V instead of -12V.

Raymond


 

On Tue, Jul 7, 2020 at 05:33 PM, Raymond Domp Frank wrote:


Just a hunch, didn't study the schematic much nor thought this through
... nor the motivation to dive into it...

Raymond


Ed Breya
 

Curiosity forced me to look at the S-52 schematics. I think Q32 is to prevent possible latch-up of the digilog circuitry during power-up. There are quite a few things going on back and forth, and with varying levels. so I can picture it maybe getting stuck during initial activation. while the supplies (including the shunt-regulated -5.1V) slew up at various rates. and the clocking system state is undefined. This is unpredictable in a mainframe, for example, with widely varying plug-in loads and combinations. It looks like once the oscillator and state control decoding are running, it should clear and cycle properly, but there may be some quasi-digilog state where the bias is partly on and the circuit is confused. I'd consider it a "power-up reset" function for now.

It could also protect against loss (permanent or temporary during power-up) of the -12.4V supply. In this event, Q32 will pull the control line down, forcing the TD bias current steering stage to dump it into ground rather than the TD. This forces a reset, regardless of the rest of the functions.

Ed


Dave Daniel
 

What is “digilog”?

On Jul 7, 2020, at 17:32, Ed Breya via groups.io <edbreya=yahoo.com@groups.io> wrote:

Curiosity forced me to look at the S-52 schematics. I think Q32 is to prevent possible latch-up of the digilog circuitry during power-up. There are quite a few things going on back and forth, and with varying levels. so I can picture it maybe getting stuck during initial activation. while the supplies (including the shunt-regulated -5.1V) slew up at various rates. and the clocking system state is undefined. This is unpredictable in a mainframe, for example, with widely varying plug-in loads and combinations. It looks like once the oscillator and state control decoding are running, it should clear and cycle properly, but there may be some quasi-digilog state where the bias is partly on and the circuit is confused. I'd consider it a "power-up reset" function for now.

It could also protect against loss (permanent or temporary during power-up) of the -12.4V supply. In this event, Q32 will pull the control line down, forcing the TD bias current steering stage to dump it into ground rather than the TD. This forces a reset, regardless of the rest of the functions.

Ed



Ed Breya
 

"Digilog" is just a term I coined decades ago, referring to circuits that are both digital and analog, sometimes without clear distinction. In reality, everything is analog, including digital circuits, until you go deep enough, then it becomes kind of digital (discrete) at the quantum level.

Ed


Tom Gardner
 

On 08/07/20 02:11, Ed Breya via groups.io wrote:
"Digilog" is just a term I coined decades ago, referring to circuits that are both digital and analog, sometimes without clear distinction. In reality, everything is analog, including digital circuits, until you go deep enough, then it becomes kind of digital (discrete) at the quantum level.
Yes. In digital circuits analogue waveforms are interpreted by the receiver to infer digital signals. Assuring that the interpretation is clear and unambiguous is termed checking the signal integrity.

But before you get to the quantum level, there are two classes of circuit that are in some senses digital: single photon avalanche detector circuits, and femtoamp  circuits.


Albert Otten
 

Thanks for the replies so far. The common thread is protection of the TD in case of other failures. I was thinking along the same lines, but also thought that one single other failure could do no harm, except perhaps a way too high +15V.
For instance a missing -12.2V would shut down U10 and U20, having the same effect as states 1 and 10-16 in normal operation. Then the TD current supply via R97+R98 would permanently be present while the TD is in the low state. That alone would do no harm I think.
I was also thinking of an interrupted R109 and hence missing -5.1V, -3V and -2.5V. That would have more or less the same effect as a missing -12.2V.
In case the zener VR109 dies (to open circuit) U10 and U20 will be destroyed but Q32 doesn't mind.

Albert


Ed Breya
 

I don't think the TD needs protection, as long as the available bias current can't get too big. Once past the peak current, the TD will switch to valley current and voltage, and should be just fine. The question then is what happens past the valley - how much current and voltage are available to continue up the diode curve, where power dissipation increases a lot. It depends on the specifics of the circuitry, which could be figured out if necessary.

I read the circuit description, and I can see how it may be possible for the bias current to get relatively quite large if things get out of control. The circuit is a sort of auto-leveling system, testing the TD during each cycle, and adjusting the arming current according to its characteristics - pretty slick, I think. The bias generator is an amplifier capable of more current than needed for operation, and its output is controlled by the TD state comparator, in kind of a sample-hold setup, with a simple long-tail pair.

If the -12.4 V supply is lost, the comparator/S-H stops working, and the amplifier goes open-loop, to whatever maximum current it can deliver, possibly risking overheating the TD. In this event, Q32 forces the current into ground instead.

Ed


Albert Otten
 

If the -12.4 V supply is lost, the comparator/S-H stops working, and the
amplifier goes open-loop, to whatever maximum current it can deliver, possibly
risking overheating the TD. In this event, Q32 forces the current into ground
instead.
Hi Ed,
When -12 V is lost, U30B will not conduct and the base of Q72 will have the proper voltage for comparator operation, like in period 2. Hence I think the TD current will not get higher than Ip. As soon as the TD fires the comparator switches Q74 to on and the TD current will drop below the arming current. The voltage at the now isolated base of Q90 will slowly drop. After that different scenarios can be thought of. The comparator may or may not switch back. The danger I think is that the average power might get too large.
Albert


Ed Breya
 

Albert,

When the -12.4 V is lost, it's essentially zero V, so the emitters of Q72 and Q74 are effectively grounded through R72, and the long-tail pair cannot provide feedback. Assuming they're Si transistors, the TD voltage can't be high enough to turn Q74 on (unless the actual TD current is very high up its diode curve, and in danger anyway). The -12.4 V emitter feed via R72 makes it able to operate around zero, and without it, it's open-loop.

Ed


 

On Wed, Jul 8, 2020 at 09:57 PM, Ed Breya wrote:


The question then is what happens past the valley - how much current and
voltage are available to continue up the diode curve, where power dissipation
increases a lot. It depends on the specifics of the circuitry, which could be
figured out if necessary.
This is the situation I had in mind in my post, though written down rather clumsily - incorrectly, actually.
There's also the situation where the -12V is - for a short or long period - between say -6V and -12V. The digilog stuff still (mostly) works but the -12V is off by a lot. Can't think the consequences through ATM.

Raymond


Albert Otten
 

You are right Ed. I overlooked that the negative supply at R72 would also be missing.

I don't remember that I have seen such a protection with an active component (so not counting clamping diodes and fuse-like resistors) elsewhere in Tek equipment, except perhaps in SMPS.

Albert

On Wed, Jul 8, 2020 at 11:26 PM, Ed Breya wrote:


Albert,

When the -12.4 V is lost, it's essentially zero V, so the emitters of Q72 and
Q74 are effectively grounded through R72, and the long-tail pair cannot
provide feedback. Assuming they're Si transistors, the TD voltage can't be
high enough to turn Q74 on (unless the actual TD current is very high up its
diode curve, and in danger anyway). The -12.4 V emitter feed via R72 makes it
able to operate around zero, and without it, it's open-loop.

Ed