7000 test/cal module(s) and backplane breakout board.


Andy Warner
 

I have a 7904A, that I intend to keep in good working order.
However, I've not seen many cal fixtures on the market and reckon the
prices are only going to go in one direction for the near future. I am
planning to design one or more cal fixture(s) using modern components. I
figure I'll learn a lot more about the scope in the process, have some fun,
share the designs, and hopefully others can find the work useful.

Step 1 in this process is a simple passive breakout board for the backplane
connections, to allow me to experiment and prototype things. I checked the
archives and did not see an existing design, so I cooked one up. The
v1 boards are just back from fab and I have uploaded some photos here:
https://groups.io/g/TekScopes/album?id=266487 I am in the process of
mounting the board in a parted-out 7A26 module frame that I had on-hand,
will update more photos as I continue (assuming there is interest.)

This board brings out the high speed signals to BNCs and the low speed
signals to screw connectors. The low speed signals are grouped roughly by
function (power, readout, IEEE-488, misc.) Be aware that for this version,
I did not match the high speed signal path lengths, or worry too much about
impedance.

I'll probably create a project page somewhere with the eagle files, the
BOM, and progress as I work on cal/test fixtures, if anyone wants to follow
along. Look for an update when I get organized enough to do that.

--
Andy


Eric
 

Andy, if you need lots of pictures of the cal fixtures let me know I have a
-01 and -02 here in the lab. I am also in process for a test board for a
7854. I had a unit arrive today.... destroyed by the shipper and bad
packing. It will at least give me something to test on. I'll be in to board
layout shortly.

On Mon, Jul 26, 2021, 10:35 PM Andy Warner <andyw@pobox.com> wrote:

I have a 7904A, that I intend to keep in good working order.
However, I've not seen many cal fixtures on the market and reckon the
prices are only going to go in one direction for the near future. I am
planning to design one or more cal fixture(s) using modern components. I
figure I'll learn a lot more about the scope in the process, have some fun,
share the designs, and hopefully others can find the work useful.

Step 1 in this process is a simple passive breakout board for the backplane
connections, to allow me to experiment and prototype things. I checked the
archives and did not see an existing design, so I cooked one up. The
v1 boards are just back from fab and I have uploaded some photos here:
https://groups.io/g/TekScopes/album?id=266487 I am in the process of
mounting the board in a parted-out 7A26 module frame that I had on-hand,
will update more photos as I continue (assuming there is interest.)

This board brings out the high speed signals to BNCs and the low speed
signals to screw connectors. The low speed signals are grouped roughly by
function (power, readout, IEEE-488, misc.) Be aware that for this version,
I did not match the high speed signal path lengths, or worry too much about
impedance.

I'll probably create a project page somewhere with the eagle files, the
BOM, and progress as I work on cal/test fixtures, if anyone wants to follow
along. Look for an update when I get organized enough to do that.

--
Andy






Andy Warner
 

Eric,
if I understand correctly, the board you are making for the 7854
isn't a replacement for the 067-0587-xx boards, but something to do with
the digital capabilities of the 7854, is that correct ?

On Mon, Jul 26, 2021 at 10:46 PM Eric <ericsp@gmail.com> wrote:

Andy, if you need lots of pictures of the cal fixtures let me know I have a
-01 and -02 here in the lab. I am also in process for a test board for a
7854. I had a unit arrive today.... destroyed by the shipper and bad
packing. It will at least give me something to test on. I'll be in to board
layout shortly.

On Mon, Jul 26, 2021, 10:35 PM Andy Warner <andyw@pobox.com> wrote:

I have a 7904A, that I intend to keep in good working order.
However, I've not seen many cal fixtures on the market and reckon the
prices are only going to go in one direction for the near future. I am
planning to design one or more cal fixture(s) using modern components. I
figure I'll learn a lot more about the scope in the process, have some
fun,
share the designs, and hopefully others can find the work useful.

Step 1 in this process is a simple passive breakout board for the
backplane
connections, to allow me to experiment and prototype things. I checked
the
archives and did not see an existing design, so I cooked one up. The
v1 boards are just back from fab and I have uploaded some photos here:
https://groups.io/g/TekScopes/album?id=266487 I am in the process of
mounting the board in a parted-out 7A26 module frame that I had on-hand,
will update more photos as I continue (assuming there is interest.)

This board brings out the high speed signals to BNCs and the low speed
signals to screw connectors. The low speed signals are grouped roughly by
function (power, readout, IEEE-488, misc.) Be aware that for this
version,
I did not match the high speed signal path lengths, or worry too much
about
impedance.

I'll probably create a project page somewhere with the eagle files, the
BOM, and progress as I work on cal/test fixtures, if anyone wants to
follow
along. Look for an update when I get organized enough to do that.

--
Andy









--
Andy


Chris Wilkson
 

Real quick...

Before you plug that into a scope, make sure your PCB edge is chamfered!
Don't plug a raw cut PCB into the scope or you have a good chance of damaging the female connector on the backplane.

Maybe the fab already did that for you, or you did it at home with a file. It's hard to tell from the photos.


Andy Warner
 

Thanks for the reminder.
Yes, I did manually chamfer the edges before inserting the board, but the
reminder is good for anyone contemplating similar experiments.
I am unsure how to request chamfered edges from OSHpark (who I use for my
prototypes), that is on my list of things to research before the next board
order.

On Tue, Jul 27, 2021 at 11:12 AM Chris Wilkson via groups.io <cwilkson=
yahoo.com@groups.io> wrote:

Real quick...

Before you plug that into a scope, make sure your PCB edge is chamfered!
Don't plug a raw cut PCB into the scope or you have a good chance of
damaging the female connector on the backplane.

Maybe the fab already did that for you, or you did it at home with a
file. It's hard to tell from the photos.





--
Andy


Chris Wilkson
 

EDIT/UPDATE...I see from the photos that you've already plugged it in. I hope you had the PCB beveled. :)
---------------
First let me say I like this project!
I wanted to do it for a long time myself and I was also targeting the 7904A.
I even got as far as buying a 7A17 prototyping plugin from Dennis.
But then the project stalled because my 7904A has some issues and I put the project (and the scope) on the shelf until "later".
It's good to see someone taking up the challenge.

The breakout PCB is a good idea. Saves wear and tear on the backplane connector.
While prototyping/testing, do you plan to mount your application circuits in the same plugin?
Or will you snake wire + cables out the front or side of the mainframe for easier access until you're happy with the test circuits?
I assume everything would be on a single PCB in the final design?

I'll be following this project. Good luck!


Andy Warner
 

For prototyping, I plan to simply snake wires out and onto the bench, at
least that's my plan until it doesn't work.

I currently have a 10-way ribbon cable snaking out so I can analyse the
readout timeslot pulses.

My plan would be to spin a PCB for whatever solution(s) I end up with.

I assume this could be adapted for the 5000 series pretty easily, but
that's not on my radar screen.

I do plan to make my work available without restriction, so others can
tweak/experiment/improve.

For instance, my plan for the readout interface is to create an SPI-based
sub-system that deals with all the current source and voltage adaptation,
so that it could be easily bolted onto any micro that can field an
interrupt and talk SPI at a reasonable rate.

On Tue, Jul 27, 2021 at 11:22 AM Chris Wilkson via groups.io <cwilkson=
yahoo.com@groups.io> wrote:

EDIT/UPDATE...I see from the photos that you've already plugged it in. I
hope you had the PCB beveled. :)
---------------
First let me say I like this project!
I wanted to do it for a long time myself and I was also targeting the
7904A.
I even got as far as buying a 7A17 prototyping plugin from Dennis.
But then the project stalled because my 7904A has some issues and I put
the project (and the scope) on the shelf until "later".
It's good to see someone taking up the challenge.

The breakout PCB is a good idea. Saves wear and tear on the backplane
connector.
While prototyping/testing, do you plan to mount your application circuits
in the same plugin?
Or will you snake wire + cables out the front or side of the mainframe for
easier access until you're happy with the test circuits?
I assume everything would be on a single PCB in the final design?

I'll be following this project. Good luck!





--
Andy


Chris Wilkson
 

I haven't used OSH Park before. But everyone knows those purple boards! (beautiful!) :)
I don't think they offer chamfering unless it's recently changed. It's been discussed in the past and it adds steps to the process (therefore cost!).

Some board houses that I know will do beveling:
Advanced Circuits does it for sure. I have used them for plug in cards before. Located in Denver, Colorado, USA. (very high quality but expensive)
Gold Phoenix does it for sure. For gold fingers they do it automatically. For solder (HASL) fingers they will do it only if you specifically ask. Located in China. (good quality, inexpensive-to-reasonable cost)
JLCPCB does it on boards > 5x5cm. I just made my first order from them but not with edge fingers. I haven't seen the boards yet, so quality is TBD. Located in China. (quality = ?TBD?, super unbelievably cheap!)


Andy Warner
 

Confirmed, OSHpark doesn't do chamfered/beveled edges, also they don't
offer hard gold as a finish, they only offer ENIG, which is not really upto
the task of many cycles. For a real run, we'd likely want to spec hard gold
finish and bevelling from a board house that can accommodate that.

However, for exploration and prototyping, I am happy with the OSHpark parts.

On Tue, Jul 27, 2021 at 11:38 AM Chris Wilkson via groups.io <cwilkson=
yahoo.com@groups.io> wrote:

I haven't used OSH Park before. But everyone knows those purple boards!
(beautiful!) :)
I don't think they offer chamfering unless it's recently changed. It's
been discussed in the past and it adds steps to the process (therefore
cost!).

Some board houses that I know will do beveling:
Advanced Circuits does it for sure. I have used them for plug in cards
before. Located in Denver, Colorado, USA. (very high quality but expensive)
Gold Phoenix does it for sure. For gold fingers they do it
automatically. For solder (HASL) fingers they will do it only if you
specifically ask. Located in China. (good quality,
inexpensive-to-reasonable cost)
JLCPCB does it on boards > 5x5cm. I just made my first order from them
but not with edge fingers. I haven't seen the boards yet, so quality is
TBD. Located in China. (quality = ?TBD?, super unbelievably cheap!)





--
Andy


Ed Breya
 

Andy wrote: "For instance, my plan for the readout interface is to create an SPI-based
sub-system that deals with all the current source and voltage adaptation,
so that it could be easily bolted onto any micro that can field an
interrupt and talk SPI at a reasonable rate."

7K readout interfacing is quite easy, once you're familiar with the details. I'd recommend using DAC-08 or DAC-10 or equivalent to drive the currents - these are an ideal match for the circuit conditions. You can also use CMOS or JFET analog switches with weighting resistors, but the DACs are more compact, and simpler to set up. You will also need to synchronize the external control stuff to the internal readout timing to know when to present the appropriate currents.

In my 7K test plug-in I started years ago, I used four (one for row, and one for column current, for each channel) DAC-08s, three CMOS logic parts, and a little diode logic, to make the readout exerciser. It presents all fifty characters on both channels, ten at a time, in a five step sequence at about one second per step. This was a simple implementation, due to using plenty of DACs, which I had in stock. Other schemes could be done, even with a single DAC and enough multiplexing/sampling/holding and such, but the beauty of these DACs is that they take care of the level shifting and current sourcing - no matter how you code and make the current signals, the actual currents need to flow from the row and column inputs into minus 15 V (or at least some negative supply).

I have a bunch of DAC-08s and -10s set aside just for readouts in custom plug-in projects. I think the MC1408 can work too. These are all oldies. There should be newer and better equivalents available. The main thing is to have 8 bits or more, current sinking output in the 1 mA FS range, and running from -15 Vee, for simplest interface.

Ed


Ke-Fong Lin
 

JLCPCB does it on boards > 5x5cm. I just made my first order from them but
not with edge fingers. I haven't seen the boards yet, so quality is TBD.
Located in China. (quality = ?TBD?, super unbelievably cheap!)
So far, I've been quite happy with all my orders with JLCPCB.
The only problem I had were cosmetic, some scratches on PCB.
You can have an idea of the board they produce: https://groups.io/g/TekScopes/album?id=243643


Andy Warner
 

My current prototype does this with 4 NPN transistors sourcing 8-4-2-1
weighted currents into a wilson current mirror, nothing harder to source
than 2N3904, 2N3906 and some E96 resistors. Time will tell whether this is
fit for purpose, as always there are plenty of ways to address this issue.

I'll crank up a proper schematic and post here.

I'm currently de-mystifying the timing of the TS<n> signals. The pulses
seem to be approx 130uS wide, negative going 0 - -15V, but the slew rate of
approx 3us/Volt, so the pulse only sits at -15V for approx 20us.
See the yellow trace on this plot:
https://drive.google.com/file/d/1d-oRC-gXE9w1Ki5tMpP8rl_hrF2QsJ_y/view?usp=sharing,
so it looks like I have around 30-40us to set up the 4 currents.
The blue trace on that plot is the derived TTL signal, mimicking the TS
interface circuit used in the 7M13. I am actively looking to change the
circuit to: a) not sit at 1.6V when "low", and switch on harder, and b)
transition faster to maximise the amount of time I have to set up the
current sinks.

On Tue, Jul 27, 2021 at 2:04 PM Ed Breya via groups.io <edbreya=
yahoo.com@groups.io> wrote:

Andy wrote: "For instance, my plan for the readout interface is to create
an SPI-based
sub-system that deals with all the current source and voltage adaptation,
so that it could be easily bolted onto any micro that can field an
interrupt and talk SPI at a reasonable rate."

7K readout interfacing is quite easy, once you're familiar with the
details. I'd recommend using DAC-08 or DAC-10 or equivalent to drive the
currents - these are an ideal match for the circuit conditions. You can
also use CMOS or JFET analog switches with weighting resistors, but the
DACs are more compact, and simpler to set up. You will also need to
synchronize the external control stuff to the internal readout timing to
know when to present the appropriate currents.

In my 7K test plug-in I started years ago, I used four (one for row, and
one for column current, for each channel) DAC-08s, three CMOS logic parts,
and a little diode logic, to make the readout exerciser. It presents all
fifty characters on both channels, ten at a time, in a five step sequence
at about one second per step. This was a simple implementation, due to
using plenty of DACs, which I had in stock. Other schemes could be done,
even with a single DAC and enough multiplexing/sampling/holding and such,
but the beauty of these DACs is that they take care of the level shifting
and current sourcing - no matter how you code and make the current signals,
the actual currents need to flow from the row and column inputs into minus
15 V (or at least some negative supply).

I have a bunch of DAC-08s and -10s set aside just for readouts in custom
plug-in projects. I think the MC1408 can work too. These are all oldies.
There should be newer and better equivalents available. The main thing is
to have 8 bits or more, current sinking output in the 1 mA FS range, and
running from -15 Vee, for simplest interface.

Ed





--
Andy


Ke-Fong Lin
 

I'll probably create a project page somewhere with the eagle files, the
BOM, and progress as I work on cal/test fixtures, if anyone wants to follow
along. Look for an update when I get organized enough to do that.
What's the height or rather width you used for your finger connector?
I had a similar project for debugging purpose (https://github.com/anotherlin/tek_7k_ext).
However, I didn't add "margin" on top and bottom, so I have to manually align the extender when inserting.
And so far, I was not able to find mechanical data from Tektronix documentation


Andy Warner
 

I used a caliper to measure several of my plug-ins, and went with my best
estimates based on that, then tested with laser cut non-functional blanks
for fit. I only just got the boards back from fab, and so far, fit and
function seem good.
When I post the eagle files, people can just reuse the dimension layer, but
I will also see about producing a dimensioned drawing for more general use.
Let me see if I can make time for that tonight.

On Tue, Jul 27, 2021 at 2:28 PM Ke-Fong Lin <anotherlin@gmail.com> wrote:

I'll probably create a project page somewhere with the eagle files, the
BOM, and progress as I work on cal/test fixtures, if anyone wants to
follow
along. Look for an update when I get organized enough to do that.
What's the height or rather width you used for your finger connector?
I had a similar project for debugging purpose (
https://github.com/anotherlin/tek_7k_ext).
However, I didn't add "margin" on top and bottom, so I have to manually
align the extender when inserting.
And so far, I was not able to find mechanical data from Tektronix
documentation





--
Andy


Ed Breya
 

Current mirrors should work fine. I presume you meant to say four PNP transistors for the DAC and level shifting from ground referenced and +5V powered TTL/CMOS. I looked at all sorts of schemes back then, and concluded that the DACs were the way to go for my needs. You can get better performance from the current mirror if you use transistor arrays. I think a CA3046 or something in that family has enough NPNs to make two mirrors.

The edges of the TS signals are intentionally very slow, to minimize interference with the sensitive circuitry - do NOT make them go faster. As I recall, the readout system makes its decision on the value either in the middle of the TS, or right at the end, when it begins to turn off. The internal clocking is not precise in frequency (you actually don't want it constant), but the relative timing of each event is exact (all digital).

Ed


Ed Breya
 

Looking at the waveform picture, I see that you're looking at speeding up the response of the TS detector, which is OK. I think I misunderstood that you were considering speeding up the actual TS edges. So, never mind about the edge speed admonition.

Ed


Andy Warner
 

I'll try and get a schematic into the computer tonight and show you what I
am thinking of.

I wasn't talking about changing the edges of the TS pulses, just my
circuit's response to those intentionally slow edges.
I want to push the bulk of the problem to firmware, so I need to field an
interrupt, figure the timeslot, and set up the correct currents before the
mainframe starts to sample the currents; nothing crazy, but if I can buy
myself more microseconds on the front end of the pulse, things can only be
good for the wider applicability of the circuit.
I couldn't find anything usable in the docs for when the row and column
currents are sampled, but looking at the pulse on a scope the window that
the -15V is valid is quite clear, so I am going to target a decent safety
margin around that.
In some later mainframe designs, it appears that the TS timing can be
shortened by certain responses from the module, so I am trying to be
conservative in my timings.

I also do not know if the readout system is similar/identical in the 5000
series (I see readouts on some 5000 displays, but have not found details of
the implementation, nor do I know how prevalent readouts were on
5000-series.) I would like to see the design easily port over to 5000s if
that is practical, even though I don't own a 5000. If there are simple
changes I can make early to accommodate, so much the better.

On Tue, Jul 27, 2021 at 3:31 PM Ed Breya via groups.io <edbreya=
yahoo.com@groups.io> wrote:

Current mirrors should work fine. I presume you meant to say four PNP
transistors for the DAC and level shifting from ground referenced and +5V
powered TTL/CMOS. I looked at all sorts of schemes back then, and concluded
that the DACs were the way to go for my needs. You can get better
performance from the current mirror if you use transistor arrays. I think a
CA3046 or something in that family has enough NPNs to make two mirrors.

The edges of the TS signals are intentionally very slow, to minimize
interference with the sensitive circuitry - do NOT make them go faster. As
I recall, the readout system makes its decision on the value either in the
middle of the TS, or right at the end, when it begins to turn off. The
internal clocking is not precise in frequency (you actually don't want it
constant), but the relative timing of each event is exact (all digital).

Ed






--
Andy


Ed Breya
 

I think you'll need at least two TS detectors (like maybe the first and last), so you can figure out the actual running frequency and interpolate the rest of the slots. In my readout exerciser, it is all inside the plug-in, and uses all of the TSs for direct coding, so it was straightforward - except for needing 14 interface signal lines.

Ed


Andy Warner
 

Simple mistake on the prototype wiring was the cause of the poor TS pulse
detection previously reported.

Here is what it should look like:
https://drive.google.com/file/d/1AqMiK25iZafHRBcBVHqfrP84sTWJQQF0/view?usp=sharing

This is basically the TS to TTL conversion circuit from the 7M13 readout
module (correctly wired this time.)

Now we have nice sharp edges, and about 35us from the rising edge of the
blue trace (the logic level output) to set up the current sinks
appropriately, which I think is plenty of time.

I am planning to use SPI port expanders, to reduce the number of I/O pins
required on the microcontroller, and also make the circuit more universal,
so I am planning to use an input pin per timeslot. The 7M13 uses a trick
where it diode ORs TS2-10 together, thus requiring only 2 pins of input,
TS1 to flag start of readout, and all the subsequent timeslots simply
increment a counter, no need for interpolation. However, I am planning to
give each timeslot its own pin, that way the circuit can diagnose missing
timeslots and other issues.

On Tue, Jul 27, 2021 at 4:39 PM Ed Breya via groups.io <edbreya=
yahoo.com@groups.io> wrote:

I think you'll need at least two TS detectors (like maybe the first and
last), so you can figure out the actual running frequency and interpolate
the rest of the slots. In my readout exerciser, it is all inside the
plug-in, and uses all of the TSs for direct coding, so it was
straightforward - except for needing 14 interface signal lines.

Ed





--
Andy


Andy Warner
 

Here is the schematic for the digitally controlled current sink:
https://drive.google.com/file/d/1VkWHA87e2c0EbP7M8WMywmGa2pkLtviQ/view?usp=sharing

That needs to be duplicated for each row/column.
Using 1% E96 resistors and unmatched transistors, it is accurate to
within +/- 10uA in my testing, so I do not think I need to resort to
matched parts.

Values of R5-R8 would need to be tweaked if your logic was 3.3V, but I plan
to design to 5V parts.

On Tue, Jul 27, 2021 at 6:26 PM Andy Warner <andyw@pobox.com> wrote:

Simple mistake on the prototype wiring was the cause of the poor TS pulse
detection previously reported.

Here is what it should look like:

https://drive.google.com/file/d/1AqMiK25iZafHRBcBVHqfrP84sTWJQQF0/view?usp=sharing

This is basically the TS to TTL conversion circuit from the 7M13 readout
module (correctly wired this time.)

Now we have nice sharp edges, and about 35us from the rising edge of the
blue trace (the logic level output) to set up the current sinks
appropriately, which I think is plenty of time.

I am planning to use SPI port expanders, to reduce the number of I/O pins
required on the microcontroller, and also make the circuit more universal,
so I am planning to use an input pin per timeslot. The 7M13 uses a trick
where it diode ORs TS2-10 together, thus requiring only 2 pins of input,
TS1 to flag start of readout, and all the subsequent timeslots simply
increment a counter, no need for interpolation. However, I am planning to
give each timeslot its own pin, that way the circuit can diagnose missing
timeslots and other issues.

On Tue, Jul 27, 2021 at 4:39 PM Ed Breya via groups.io <edbreya=
yahoo.com@groups.io> wrote:

I think you'll need at least two TS detectors (like maybe the first and
last), so you can figure out the actual running frequency and interpolate
the rest of the slots. In my readout exerciser, it is all inside the
plug-in, and uses all of the TSs for direct coding, so it was
straightforward - except for needing 14 interface signal lines.

Ed





--
Andy





--
Andy