Date   
What is the meaning of ULU? Topic was: 7000-series power-hungry plug-ins

 

On behalf of all of us thank you Håkan once again.

Of course I know what Fold Back Current Limiting is. In its simplest terms it is a circuit that prevents you from burning up a valuable instrument while you are tinkering around inside it with a screwdriver or other metal tool. One of Murphy Law's guarantees that the more careful you are, the more catastrophic the damage you will cause. Fold back Current Limiting is designed to sacrifice active devices such as transistors and ICs in order to protect the fast blow fuse from stress.

"tinkera123" also asked what the acronym ULU meant. I was hoping someone would explain it. The specific sentence it is used in doesn't give much to go on:
"Some suggestions for the wiring interface to the ULU are offered."
This is followed by 5 suggestions.

From the suggestions it sounds like they are talking about a Device Under Test but the well-known acronym for this is DUT. Some companies use Unit Under Test or UUT.

So far no one has offered an explanation for ULU. I can't think of anything that fits those letters and there are very few ULU acronyms.

The closest I could up with is Unit Under Load which might mean a set of standard load resistors attached to a male connector that plugs into the backplane and loads the power supply enough to draw the maximum amount of power from each supply that the slot should be able to supply. But a Unit Under Load would be UUL. As anyone who plays Scrabble knows, the order of the letters can be really important.

Dennis Tillman W7PF

-----Original Message-----
From: TekScopes@groups.io [mailto:TekScopes@groups.io] On Behalf Of
tinkera123
Sent: Friday, October 12, 2018 3:34 PM
Subject: Re: [TekScopes] 7000-series power-hungry plug-ins

Regarding this pdf of 7000 series currents ..... I am unfamiliar with the
terms Foldback currents and ULU.
Can some-one please explain??

-Chuck Harris

PS, thanks to Håkan for the 7904 power supply capacity note.


--
Dennis Tillman W7PF
TekScopes Moderator

Re: 2445A calibration

Harvey White
 

On Sat, 13 Oct 2018 18:45:03 -0400, you wrote:

PHK is an open source legend. His disassembler is available
for free on github.
THe internet is being particularly obtuse tonight, or at least
duckduckgo is...

Have a name I should look for? Perhaps that'll help.

Sorry, and thanks.

Harvey



PHK wrote the NTP routines for openbsd.

-Chuck Harris

Harvey White wrote:
On Sat, 13 Oct 2018 16:05:14 -0400, you wrote:
...

PHK, Poul-Henning Kamp wrote a nice one that actually analyzes the code
by executing it. He used it to disassemble the code in some HP counters.
Hmmm, some people want money for those things, not that I begrudge him
the income, but I tend to go to open source.

That's what mine does, although I get tired of writing tools to make
tools....



...

IIRC, the 6802 did more integration of the RAM into the processor. I
think that the DM5010 uses one as well
Tek tended to use the 68B02, which is a 6802 without the internal RAM.
The one in the DM5010 isn't, I think, and actually has internal RAM.
For analysis cases, all it does (of course) is to change the location
of some of the RAM.

Harvey


-Chuck Harris






Re: What is the meaning of ULU? Topic was: 7000-series power-hungry plug-ins

Renée
 

I love the definition of "Fold Back Current Limiting " ...Dennis you are so right, the fuse always survives...LMAO....thanks I needed that...
Renée, K6FSB

On 2018-10-13 05:49 PM, Dennis Tillman W7PF wrote:
On behalf of all of us thank you Håkan once again.

Of course I know what Fold Back Current Limiting is. In its simplest terms it is a circuit that prevents you from burning up a valuable instrument while you are tinkering around inside it with a screwdriver or other metal tool. One of Murphy Law's guarantees that the more careful you are, the more catastrophic the damage you will cause. Fold back Current Limiting is designed to sacrifice active devices such as transistors and ICs in order to protect the fast blow fuse from stress.

"tinkera123" also asked what the acronym ULU meant. I was hoping someone would explain it. The specific sentence it is used in doesn't give much to go on:
"Some suggestions for the wiring interface to the ULU are offered."
This is followed by 5 suggestions.

From the suggestions it sounds like they are talking about a Device Under Test but the well-known acronym for this is DUT. Some companies use Unit Under Test or UUT.
So far no one has offered an explanation for ULU. I can't think of anything that fits those letters and there are very few ULU acronyms.

The closest I could up with is Unit Under Load which might mean a set of standard load resistors attached to a male connector that plugs into the backplane and loads the power supply enough to draw the maximum amount of power from each supply that the slot should be able to supply. But a Unit Under Load would be UUL. As anyone who plays Scrabble knows, the order of the letters can be really important.

Dennis Tillman W7PF

-----Original Message-----
From: TekScopes@groups.io [mailto:TekScopes@groups.io] On Behalf Of
tinkera123
Sent: Friday, October 12, 2018 3:34 PM
Subject: Re: [TekScopes] 7000-series power-hungry plug-ins

Regarding this pdf of 7000 series currents ..... I am unfamiliar with the
terms Foldback currents and ULU.
Can some-one please explain??

-Chuck Harris

PS, thanks to Håkan for the 7904 power supply capacity note.

Re: What is the meaning of ULU? Topic was: 7000-series power-hungry plug-ins

Harvey White
 

On Sat, 13 Oct 2018 19:32:21 -0700, you wrote:

I love the definition of "Fold Back Current Limiting " ...Dennis you are
so right, the fuse always survives...LMAO....thanks I needed that...
Renée, K6FSB
What happens in a technical sense is that the circuit is set up with a
(much lower) short circuit current limit. When the overcurrent
happens, the circuit "folds back" to the point where the maximum
current is the foldback limit. To get it to reset, you generally turn
power off and reapply power.

There's a particular setup in the uA723 regulator (yeah, old
nomenclature) that is available for that.

An example would be that you have a 5 volt supply at 1.5 amps,
foldback to 300 ma.

Voltage is reduced, of course, to maintain that maximum current.

The old data sheets for the UA723 would show that circuit. A nice
thing is that these regulators show up in Tektronix equipment.

and I *think* that a suitable quote runs something like this:

Fuse: an inexpensive part designed to fail to protect a circuit; is
always protected by an extremely expensive part that will fail first
in order to protect the 25 cent fuse.

Harvey




On 2018-10-13 05:49 PM, Dennis Tillman W7PF wrote:
On behalf of all of us thank you Håkan once again.

Of course I know what Fold Back Current Limiting is. In its simplest terms it is a circuit that prevents you from burning up a valuable instrument while you are tinkering around inside it with a screwdriver or other metal tool. One of Murphy Law's guarantees that the more careful you are, the more catastrophic the damage you will cause. Fold back Current Limiting is designed to sacrifice active devices such as transistors and ICs in order to protect the fast blow fuse from stress.

"tinkera123" also asked what the acronym ULU meant. I was hoping someone would explain it. The specific sentence it is used in doesn't give much to go on:
"Some suggestions for the wiring interface to the ULU are offered."
This is followed by 5 suggestions.

From the suggestions it sounds like they are talking about a Device Under Test but the well-known acronym for this is DUT. Some companies use Unit Under Test or UUT.
So far no one has offered an explanation for ULU. I can't think of anything that fits those letters and there are very few ULU acronyms.

The closest I could up with is Unit Under Load which might mean a set of standard load resistors attached to a male connector that plugs into the backplane and loads the power supply enough to draw the maximum amount of power from each supply that the slot should be able to supply. But a Unit Under Load would be UUL. As anyone who plays Scrabble knows, the order of the letters can be really important.

Dennis Tillman W7PF

-----Original Message-----
From: TekScopes@groups.io [mailto:TekScopes@groups.io] On Behalf Of
tinkera123
Sent: Friday, October 12, 2018 3:34 PM
Subject: Re: [TekScopes] 7000-series power-hungry plug-ins

Regarding this pdf of 7000 series currents ..... I am unfamiliar with the
terms Foldback currents and ULU.
Can some-one please explain??

-Chuck Harris

PS, thanks to Håkan for the 7904 power supply capacity note.


Re: 2445A calibration

Chuck Harris
 

You could try:

<https://github.com/bsdphk/PyRevEng>

-Chuck Harris

Harvey White wrote:

On Sat, 13 Oct 2018 18:45:03 -0400, you wrote:

PHK is an open source legend. His disassembler is available
for free on github.
THe internet is being particularly obtuse tonight, or at least
duckduckgo is...

Have a name I should look for? Perhaps that'll help.

Sorry, and thanks.

Harvey

Re: 468 horizontal jitter

skv1958@...
 

Hi, I am a new comer in the forum with little experience, but I have tried fixing various problems my old 465B had. It's channel 1 had jitter, the trace vertically changing position at random, by about half a division, with or without signal being applied. I could see edges of the rise or fall and the edges we're fast. I suspected a semiconductor device initially, but finally I traced the problem to vertical centering pot on vertical preamplifier board, a Bourns 3352. Replacing the pot cured the problem. In fact almost all other problems of the scope were traced to failed or failing pots of same family. I have replaced 11 pots so far, and 6 more are suspected on trigger generator board. Surprisingly, other brand pots are all fine. Do look around for failing pots. May be this is of some help for your problem.

Shailendra

Re: 468 horizontal jitter

Brendan
 

On Sat, Oct 13, 2018 at 10:38 AM, lop pol wrote:

I'm working on my second 468 and I noticed some horizontal jitter.

On Sat, Oct 13, 2018 at 09:51 AM, Jeff Urban wrote:


In case you haven't, it is important to check if it is a centering problem
or
a triggering problem. Even in auto or free run it is still triggered, so if
it
is the problem could be all the way back at the ramp generator.

If the trace itself is moving and not the sweep (I hope you got that...)
then
I would more look for hash on a PS line somewhere. Of course that applies to
the ramp generator as well but different PS legs of course.
Thanks Jeff.
There is jitter on the A gate out with no input just a free running trace. I
had to put my 465 in 10x to see it but it does match the jitter on the 468.
So... This looks like its going to be a fun one to figure out.
Q181 on the sweep and z axis board was not seated properly. I have no idea how it happened. I have never messed around inside but the base was bent instead of seated. Looking at the schematic I can't tell how that could cause the trace jitter though. The base is connected to ground. So far it seems to be working correctly though. I also installed the EPROMs and images from the Vintage Tek museum. Boards fit correctly and so far so good.

Re: 2445A calibration

Harvey White
 

On Sat, 13 Oct 2018 23:11:02 -0400, you wrote:

You could try:

<https://github.com/bsdphk/PyRevEng>
Thanks, downloading and I will evaluate it.

Wouldn't have thought of that one. Mine's written in Lazarus Pascal,
which is my preferred "goto" for windows style programming.

For microprocessors (ARM), it's C (because a certain company does not
generate a C++ project at all).

Harvey


-Chuck Harris

Harvey White wrote:
On Sat, 13 Oct 2018 18:45:03 -0400, you wrote:

PHK is an open source legend. His disassembler is available
for free on github.
THe internet is being particularly obtuse tonight, or at least
duckduckgo is...

Have a name I should look for? Perhaps that'll help.

Sorry, and thanks.

Harvey

Re: 2445A calibration

maxim.vlasov@...
 

After the code disassembly, seeing that the FW writes 0xAC to the DAC for the U2521 channel 0, the reference voltage on TP2421 is supposed to be 1.24692V
but I measure TP2421=-1.2524V, which is 4392ppm lower. I wonder how accurate it supposed to be.

Try to socket tomorrow U2420 and measure the resistors R2422, R2421, R2521 & R2520 separately.

One way of attack would be by using the Logic Analyzer to find the corresponding to CAL02 routine code and understand it in the details (I'm moving forward with IDA disassembly).

The other - a bit more simplistic - by using the LA to decode/demultiplex the digital sequence at the input of the DAC and multiplexers. It's assumed that in the static o-scope operation, the levels produced by the multichannel DAC are static. Hence, I could compare the code written to the DAC and the de-mulitplexer against the voltage setting at the output. For that there is Agilent 16702a+16534a+16710a setup on my bench. However, I believe that once the voltage settings will be proven static after de-multiplexing, the high resolution voltmeter will be required to find whether the output corresponds to the input digital settings.

Also even more interesting exercise can be done to analyze the performance of the multichannel successive approximation ADC. I try connecting the LA to the DAC, U2510 comparator output (to be socketed too) or even the port 3 input buffer U2220 and the multiplexer controls for U2401, U2601 & U2501. Again, assuming that the input to the ADC at the runtime is static for some signals, use those to find the end of conversion value (also this would help understanding the successive approximation FW routine).

Re: PG 506 IS IT NECESSARY FOR CALIBRATING?

Albert Otten
 

On Fri, Oct 12, 2018 at 12:54 AM, Jim Olson wrote:


This is for the folks here that are a lot more knowledgeable and experienced
than me with these 4xx series scopes with the testing and calibrating of them.
I have a number of the TM series plugins plus case for them that I got really
lucky and got for a great deal. Here's a list of the modules: DM501, DM502A,
PG501, PG502, PS503A, FG504, Type 187 Time mark Generator, Type 191 Signal
Generator and a CT3, need to get the BNC adapters for it I see there two types
one straight through and one with a 50ohm terminator should i get both? I
still need the 50ohm terminators and coax cables. I have 100' of RG58U just
need to pick up some cable connectors for it.
I also have a good 2215 scope with a P6208 probe.
So my question is do I need the PG506 to really calibrate the scopes and also
should i get a SG503 to get the higher Mhz output?
Once i get the 466 together I will really need to calibrate it so do i have
enough cal instruments? and I will be asking for much help too!

Jim O
Jim,

What you miss in your series of plugins is the possibility of quick DUT V/div checks, i.e. you miss the Standard Amplitude mode of the PG506.
The PG502 is fast enough (rise time) and flat (pulse top flatness) to replace the PG506 for waveform checks.

The Type 191 is sufficient to check the frequency response up to 100 MHz, so good enough for a 466. You might be curious how much higher the 466 goes; then of course you need a SG503 or similar.

I use the 50R feed through terminators 011-0049-01. But for a 100 MHz scope a T-connector with an arbitrary 50R end stop in one leg will do. I gathered some end stops when the local computer coax network at my work was dismantled.

Albert

Re: What is the meaning of ULU? Topic was: 7000-series power-hungry plug-ins

 

On Sun, Oct 14, 2018 at 02:49 AM, Dennis Tillman W7PF wrote:


So far no one has offered an explanation for ULU. I can't think of anything
that fits those letters and there are very few ULU acronyms.
How about Universal Load Unit referring to the 067-fixtures mentioned
in the headline of the first page.
/Håkan

Re: Tek 2467B

BryanByTheSea
 

I did it and it went bad, not sure what happened, but I believe the voltage got pulled too low when using the programmer to read and it erased/corrupted the DS1225. Possibly the control IC itself relies on the backup battery voltage being above a certain level or it fails to pass the chip select signal through. In hindsight I should have taken screenshots of the memory displayed from the CRT, can't remember what option, but at least I would have had some type of backup.

Re: 2445A calibration

Siggi
 

On Sun, 14 Oct 2018 at 04:42 <maxim.vlasov@...> wrote:

After the code disassembly, seeing that the FW writes 0xAC

Funny, this is two codes off from my derivation of the voltage, from
assumed 1.36V & -1.25V references. This is a 12 bit DAC, do you ever see
the remaining nibble written?


to the DAC for the U2521 channel 0, the reference voltage on TP2421 is
supposed to be 1.24692V
but I measure TP2421=-1.2524V, which is 4392ppm lower. I wonder how
accurate it supposed to be.
R2520/2521 are both specified 0.5%, and so is R2013, although that one is
additionally specified for low TC. Assuming R2013 and R2521 track
reasonably in temperature, given the trimming you should be able to get
well under 0.5% accuracy.

Now, the DAC calibration procedure is actually against J119 pin 13, which
looks to be the DLY REF 0 output from the A5 board. Maybe you have leaky
S&H caps or something dragging on that line, pulling your calibration to
one side? Note that the DLY REF outputs are pretty high impedance. If you
have something dragging on the line, you'd see U2620B railing to one side
or the other...

Re: 2465B Blue Screen Filter - 378-0270-00

tekscopegroup@...
 

Victor kindly please advise me via email once your filters are available for purchase on ebay as you indicated. Thanks. -Alex

Re: 2445A calibration

maxim.vlasov@...
 

Siggi,

In the given code snippet, the X register is 16 bit and the full 16 bit write is performed. The DAC port has two bytes: 0x87F for the MSByte and 0x880 for the LSByte. The X register is loaded with the 0x00AC absolute value.
As we look at the bits of the MSByte (0x87F), the bit 7 is the interrupt interval counter/timer reset control. The bits 4-6 are the channel code selects for the demultiplexer.
BTW, as you can see in some other examples, the DAC is accessed in parts. But I've seen a few places (could only find it by LA) where the DAC is addressed indirectly and the Tek programmers even use the stack pointer as the register to write the data into the DAC!!! The code is scarce indeed and was written different programmers.

And you are exactly to the point, IMHO, that if I follow the DAC calibration procedure, the DAC is railing indeed to the right side or even just a bit smaller. Can put the delta cursor over the 11th vertical division or a bit further right! Therefore I also assumed that there is something weird with the DAC and something is dragging the line.
I'll measure all the resistors and levels with 6.5 digit multimeters and re-calculate the values and voltages. Logically if this is not the resistors then either the caps or the DEMUXers and/or OPAMPS.
Even a small leakage in the de-muxer will create the voltage offset.
So the goal is check the DAC reference circuit in the first step, since now the digital part of the circuit behavior is known.

Re: 2445A calibration

maxim.vlasov@...
 

I little type: instead of "Can put the delta cursor over the 11th vertical division or a bit further right!", please read "I can't put the delta cursor over the 11th vertical division or a bit further right!"

Re: 2445A calibration

maxim.vlasov@...
 

"I little type" -> A little typo

bloody autocorrector!

Re: 2445A calibration

Chuck Harris
 

I have always been afraid to look into the ROM on these scopes.

I like to think nice thoughts of Tektronix, but there really is
no excuse for the rough edges the "A" and "B" scopes have...

Maybe you will be the one to fix the warts that Tektronix's
bean counters forced engineering to leave behind?

One thing, if you can move the cursor past the bounds of the graticule,
you have found your problem.

That can only really happen if the vertical/horizontal amplifiers
are not calibrated to match up with the graticule lines on the
CRT.

If the horizontal/vertical amplifiers are not calibrated to match
up with the graticule lines, the vertical attenuator steps, and the
horizontal time/div settings will always give LIMIT readings, which
is what you are seeing.

Go back and do the CRT ADJUSTMENTS section, CAL 01, and CAL 02 again.

The CRT ADJUSTMENTS section is the basis for everything to do with
showing pretty green lights on the screen in a linear undistorted
fashion.

If the cursors overrun the horizontal graticules, you have likely
botched the first step of CAL 01.

If the cursors overrun the vertical graticules, you have likely
botched the first step of CAL 02.

Think through how you do them again, and ask questions if something
confuses you at all. If you get these steps wrong, you have no hope
of ever getting rid of the LIMIT error.

-Chuck Harris


maxim.vlasov@... wrote:

Siggi,

In the given code snippet, the X register is 16 bit and the full 16 bit write is performed. The DAC port has two bytes: 0x87F for the MSByte and 0x880 for the LSByte. The X register is loaded with the 0x00AC absolute value.
As we look at the bits of the MSByte (0x87F), the bit 7 is the interrupt interval counter/timer reset control. The bits 4-6 are the channel code selects for the demultiplexer.
BTW, as you can see in some other examples, the DAC is accessed in parts. But I've seen a few places (could only find it by LA) where the DAC is addressed indirectly and the Tek programmers even use the stack pointer as the register to write the data into the DAC!!! The code is scarce indeed and was written different programmers.

And you are exactly to the point, IMHO, that if I follow the DAC calibration procedure, the DAC is railing indeed to the right side or even just a bit smaller. Can put the delta cursor over the 11th vertical division or a bit further right! Therefore I also assumed that there is something weird with the DAC and something is dragging the line.
I'll measure all the resistors and levels with 6.5 digit multimeters and re-calculate the values and voltages. Logically if this is not the resistors then either the caps or the DEMUXers and/or OPAMPS.
Even a small leakage in the de-muxer will create the voltage offset.
So the goal is check the DAC reference circuit in the first step, since now the digital part of the circuit behavior is known.

Re: 2445A calibration

Siggi
 

On Sun, 14 Oct 2018 at 09:34 <maxim.vlasov@...> wrote:

And you are exactly to the point, IMHO, that if I follow the DAC
calibration procedure, the DAC is railing indeed to the right side or even
just a bit smaller. Can put the delta cursor over the 11th vertical
division or a bit further right! Therefore I also assumed that there is
something weird with the DAC and something is dragging the line.
My point is that the DAC calibration procedure is performed against the DLY
REF 0 output of the A5 board. If everything's OK, this should be directly
buffering the DAC's (voltage converted) output. If the DLY REF 0 output is
off for any reason, the calibration procedure will propagate that error
back to the DAC's calibration, and everything else will be out from that
point forward.

I've no idea whether this is the case, but you can test this by looking at
U2620B (or whichever op-amp is the buffer for DLY REF 0 on your A5). Just
put a scope against the hold capacitor, see whether it's holding steady.
Then look at the output of the op-amp as you run the delay control from one
end of the range to the other. If you see the op-amps output jump to one
rail or the other, you'll know there's something up with that line.
Notice that due to the diodes CR2620/2630 and the resistors going to +5/-5V
and GND, there's no way for the op-amp to directly drive this line. It can
only sink the current from R2621 to drop the voltage on the line, so this
output is high impedance and therefore relatively easy to muck up.
On the A1 board there are decoupling capacitors on the DLY lines,
C851-C854, and ISTR cases where those caps have gone leaky and dragged on
the A5 outputs.

Re: 2445A calibration

maxim.vlasov@...
 

Chuck,

Regarding the ROMs it's certain that the thing is hand-written in ASM (but not macro ASM). Looks like the work was spliced between the team and they have put almost the double effort into creating the infrastructure 2 or even more times. They could simply create the common low level drivers and put all of them together with the interrupt service routines into the lower RAM working area or at least use the macro ASM and use the same code modules for the time critical applications. But they have prefered another way of doing things. Or maybe the current state of the project is the result of a long and painful evolution (usually when things are getting pretty ugly at the end). Also the code hierarchy and the depth of the nesting is limited by the stack heap size, which is also sitting in the bottom 2K area.
I'm nobody to judge the mighty Tek decisions, but I would make the system more simple. One of the complexities in the current FW are due to the fact that there is no common always "visible" ROM area with the interbank calls and routines. Also it would be good to keep the interrupt vectors in RAM (just give the ROM under reset) especially since there is plenty of free space at the end of each 32K ROM partition.
But at the end looks like apart from jumping all over the place the thing is well debugged (the most important) and does its function.

Also thank you for pointing to the screen adjustment, which I have always skipped. I'll start from that and check out again whether I can put the cursor beyond the bound of the graticule after that. Regarding the ripple, what was measured on J119 is well in the spec (almost no ripple at all).

Thanks again,