Date   

Re: 475A Chop Blanking and a Theory Question

Chuck Harris <cfharris@...>
 

In the early days of tektronix, the model number of a scope
incorporated the size of the CRT.

200 series was 2" diagonal.
300 series was 3" round, or diagonal.
400 series was 4" round, or diagonal.
500 series was 5" round, or diagonal.

As time went on, the relationship between model number and
screen size became more and more abstract.

Then came the 7000 and 5000 series, and all bets were off.

-Chuck Harris


Raymond Domp Frank wrote:

There's so much talk about "the 400 series" and "the 2000 series". It suggests a model numbering distinction that doesn't exist.

Apart from the 485 vs. the 455/465/466/468, which I have difficulty calling one "series", there are other 400-numbered 'scopes: The 453 and 454 and their A-varieties and the 422 (15 MHz, year of introduction 1966) come to mind. Very different beasts, not much more in common than the model number format "4xy".


Re: 475A Chop Blanking and a Theory Question

 

On Sat, Dec 19, 2020 at 08:48 AM, Jeff Dutky wrote:


Not to sell the 5000 series scopes short: I keep thinking that I need one just
to have a large X-Y display around
If you think about going that path, don't forget the 7603. The 7000 family is so much more powerful, interesting and versatile than the (low-cost) 5000 series.

Raymond


Re: 1S1 sampling bridge GaAs diodes: What alternatives?

leonard scheepsma
 

Right Tom!
:-)


Re: 475A Chop Blanking and a Theory Question

Harvey White
 

Nobody designs them in, but they do have to be thought of in the design process, which was my thought.

Tektronix did (I think) and I know a lot of people in the 70's and 80's (for various copy protection schemes, as well as the OIASC (Oh I Am So Clever) effect), who used in assembly language the practice of jumping into the middle of a 3 byte instruction. The two bytes that were the address part were important, but the whole 3 byte instruction, while valid, did nothing useful.

When disassembling early Tek assembly language, some things like this may need to be considered.

Harvey

On 12/19/2020 4:49 PM, Jeff Dutky wrote:
Harvey,

I've never known anyone to design memory leaks into the intentional performance of their system.

I've been a little obsessed with this idea since, however, and I might have some ideas of software analogs:

1. cache effects on array traversal (row major traversal is SLOW, but column major traversal is fast, or vice versa)

2. index selection in SQL queries (at one time the order of terms in the selection criteria affected what indexes could be used)

3. Duff's Device (abuse of a C case statement partially embedded in a loop for loop unrolling)

4. (longish story) My father worked as a service engineer for Varian MAT in the late seventies, then as a self-employed consulting engineer through the 80s. When he first worked at Varian he and a colleague worked on a program for the 620 series of minicomputers to plot mass spectra on Tektronix 4010 terminals. In the 80s he was asked by a client to modify the program (called S-PLOT) to run from a different location in memory. He ran into difficulty because his colleague had reused specific instructions as constant values elsewhere in the program, and if you relocated the program you might change an offset in an instruction word that was also being used as a non-address constant by some other part of the program. I helped him comb through the code for jump instructions that needed to be relocated, but the omnipresent threat of munging a reused word value has informed my appreciation of the inherent problems with analyzing and debugging computer programs.

I would question any of these practices if I encountered them in a code review. At the very least these uses would require extensive documentation, but I'd be giving the programmer some serious side-eye if they didn't rewrite the code to avoid this kind chicanery.

-- Jeff Dutky





Re: 475A Chop Blanking and a Theory Question

 

On Sat, Dec 19, 2020 at 10:49 PM, Jeff Dutky wrote:


I've never known anyone to design memory leaks into the intentional
performance of their system.
I still can't believe the mess caused by memory leaks and buffer overflows that plagued MS Win software at some time. It was so omnipresent that one could have mistaken it for being intentional, or was it just the "fair weather programming culture"?

Raymond


Re: 475A Chop Blanking and a Theory Question

 

There's so much talk about "the 400 series" and "the 2000 series". It suggests a model numbering distinction that doesn't exist.

Apart from the 485 vs. the 455/465/466/468, which I have difficulty calling one "series", there are other 400-numbered 'scopes: The 453 and 454 and their A-varieties and the 422 (15 MHz, year of introduction 1966) come to mind. Very different beasts, not much more in common than the model number format "4xy".

Something similar applies to what has been called "the 2000" series in this thread: Just talking about cases, within the 2200-series, most are quite similar but the 2245/2246/2247/2252's are taller (higher). They also have a very different internal construction (from the below-224x models).

Then there are the 23xx 'scope models.

Next are the 24xy models, with digital 243x and 2440, and analog above that number.

Then there's the 27xy-series, but these are spectrum analyzers.

There is more...

Raymond


Re: 475A Chop Blanking and a Theory Question

 

Harvey,

I've never known anyone to design memory leaks into the intentional performance of their system.

I've been a little obsessed with this idea since, however, and I might have some ideas of software analogs:

1. cache effects on array traversal (row major traversal is SLOW, but column major traversal is fast, or vice versa)

2. index selection in SQL queries (at one time the order of terms in the selection criteria affected what indexes could be used)

3. Duff's Device (abuse of a C case statement partially embedded in a loop for loop unrolling)

4. (longish story) My father worked as a service engineer for Varian MAT in the late seventies, then as a self-employed consulting engineer through the 80s. When he first worked at Varian he and a colleague worked on a program for the 620 series of minicomputers to plot mass spectra on Tektronix 4010 terminals. In the 80s he was asked by a client to modify the program (called S-PLOT) to run from a different location in memory. He ran into difficulty because his colleague had reused specific instructions as constant values elsewhere in the program, and if you relocated the program you might change an offset in an instruction word that was also being used as a non-address constant by some other part of the program. I helped him comb through the code for jump instructions that needed to be relocated, but the omnipresent threat of munging a reused word value has informed my appreciation of the inherent problems with analyzing and debugging computer programs.

I would question any of these practices if I encountered them in a code review. At the very least these uses would require extensive documentation, but I'd be giving the programmer some serious side-eye if they didn't rewrite the code to avoid this kind chicanery.

-- Jeff Dutky


TEK176 fixing a shorted wet tatalum capacitor

Miguel Work
 

The first time that I look 176 inside I knew that some of his 50 wet tatalum capacitor will fail. I have uploaded some photos.

https://groups.io/g/TekScopes/album?id=258302







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Re: 475A Chop Blanking and a Theory Question

Jim Ford
 

Yep, I worked as a circuit board designer for an IC design company for over 10 years, and I drew a few conclusions about the difference between PCB  and chip design.  Essentially there's no inductance on-chip; the lengths are so small.  If you need inductance, it will take lots of chip area = expensive, and the inductors will be lousy (low Q, compared to discrete components on a board). OTOH, on-chip you have to be concerned with shunt resistances because silicon is much more conductive than PCB dielectric material.  Only on critical boards that have nA or pA currents do you even care about shunt resistances.  Chip design is also one-sided, building up from the substrate, vs. board design being two-sided, building out in even numbers of metal layers from a double-sided core.  Many more differences I'm sure.  Then there's package design, which bridges the two....     Jim Ford Sent from my Verizon, Samsung Galaxy smartphone

-------- Original message --------From: "Dave Peterson via groups.io" <davidpinsf=yahoo.com@groups.io> Date: 12/19/20 10:22 AM (GMT-08:00) To: TekScopes@groups.io Subject: Re: [TekScopes] 475A Chop Blanking and a Theory Question My $0.02 as an IC circuit designer:We call it parasitic capacitance. But any and all physical implementations of every element of a circuit has parasitic resistance, capacitance, and inductance. Sometimes even parasitic active components. Latchup is when parasitic BJTs in a CMOS circuit get turned on shorting power & ground. Very bad. Can let the magic smoke out. I recall Stanford graduate students doing studies on the effects of parasitic inductance on the clock circuits of Pentium and above class designs. Would Giga-Hertz clocks even work? How would timing be matched and closed across the device? At the time it was not a sure thing at all and it took a fair amount of analysis to understand.Absolutely the Tek engineers would be accounting for parasitics in the physical design. The legions of engineers coming in to work are largely involved in "back-end" analysis. The design engineering positions are the most sought after coveted positions and usually achieved after serving some time in a back-end role. They account for a relatively small number of the design staff. A large cost of product development is the license fees for the extraction and analysis tools that verify the design after including the physical implementation. In the IC world these are provided by Synopsys and Cadence, FWIW.My ignorant opinion is that I doubt the orthogonal position of components on a board is considered significant to parasitics. That's not to say all 3 dimensions aren't considered in parasitic analysis, but there is a fair amount of disregarding of "insignificant" parasitics. For example, extraction software has minimum value settings for capacitors and resistors extracted from a physical layout. Resulting network size impacts simulation run time and must be balanced as part of the back-end analysis. The larger the analysis the greater the approximations. Generally, in IC layout, inductance is not extracted at all. To give a sense of how significant disregard is as part of parasitic extraction.I would not be too concerned about moving the standing position of components too much. To a reasonable extent. I wouldn't go pushing over the vertical series connected resistors, etc. I get why the physical implementation of series resistors distributes the cap more, so would impact frequency response. I wouldn't have thought of that if our more experienced members hadn't brought it up. But I would suspect generally moving components apart is better than otherwise. The designers likely would minimize the impact of parasitic capacitance caused by component proximity. If they needed the capacitance there would be more repeatable means of including it. Field documentation would be explicit about specifying the requirements. I'd think.But I'm a newb. Just thought I'd chime in on parasitics and how significant they can be, while also disregarded to some extent.Dave


Re: So how does this hobby work now?

Jean-Paul
 

Bonjour à tous, a few Tektronix Memories......

In 1967, as a young engineer about to graduate, I was invited for a summer at Lawrence Radiation Laboratoires. I was touring the Livermore lab, in fusion power area, an experiment running a pinch or toroid plasma....huge components, like energy storage capacitors and RF plumbing.

In a shed, a 5 m rolling door, labeled DANGER HIGH VOLTAGE . I was Very curious.....thru thick windows were rows of DOZENS of TEKTRONIX 500 series scopes lined up.

The physicist explained that rack of scopes behind the door were elevated at 20 kV. Many safety interlocks.
The scopes were preset, the HV turned on, the experiment ran ( they called each transient a "shot") and scope cameras recorded the results. My first mémoire of Tektronix scopes.

By 1968, at my first job, designing real time Spectrum Analyzers, 454 began to replace the 500 tube scopes.

Jon


Re: So how does this hobby work now?

Greg Muir
 

Tom, Michael,

In the past I had times when becoming rather stuck in an analog design where I had to reach out for help. Fortunately I had the opportunity to either call Jim Williams or email Bob Pease about a problem that I felt I was totally clueless on. And the comment in the article regarding Jim’s need to answer every call is very true. He always seemed to have the time to devote to really helping people with questions.

As for Bob Pease there was always a multi-page email answer full of comments, suggestions and new approach ideas to try frequently along with PDFs of past application notes from his library.

The passing of both men is a stupendous loss to the engineering community. And the loss of Bob’s life was unnecessary given his death occurring while attending Jim’s funeral.

Greg


Re: So how does this hobby work now?

Greg Muir
 

Gordian,

A very refreshing story indeed about your international venture and unexpected cooperation from the Tektronix people. Both Tek and HP were the true companies of past willing to help people with whatever they needed.

I experienced a couple of events when working with a National Science Foundation offshoot back in the mid 80’s. One was working on development of CCD sensors to be part of a high dispersion spectrograph for stellar astronomy. The entire unit was built in-house. The CCD arrays turned out to be a real challenge to meet necessary low light level detection specifications (finally resulting in having only 10 electrons read noise) as they operated in their cryogenic environment.

After a considerable search I happened upon TriQuint Semiconductor – a child of Tektronix at the time located on the Tek campus in Beaverton. At that time they were developing some very esoteric CCD arrays for military uses. A simple phone call to their engineering people resulted in an invite to visit their facility and discuss my needs.

Upon meeting with the engineers I laid out the design specifications to be met that included no cover on the Kovar housing to prevent spectral shaping and flipping the silicon die over on its back so as to minimize the travel of the spectra through the material to minimize fringing. And I was surprised to receive the answer “no problem.” These people were willing to do what was necessary to meet the customer’s specifications.

One of the memorable parts of the trip was wandering through the Tek facilities. I was invited on a tour by the TriQuint manager I had met. It happened that corporate had squeezed the (then) small TriQuint operation in one of their CRT manufacturing facilities. I remember when going to their offices I had to duck under the continuous stream of unfinished CRT glass envelopes traveling on the overhead conveyors on their way to final assembly. It was interesting to take in all of the busy employees as they diligently worked to produce their top quality products.

When the trip was coming to a close I was invited out to dinner with the TriQuint manager. Expecting simply a good meal and conversation I was astounded when He offered a position in their organization. But unfortunately the timing was not right given the complex task I had presently been involved in. An opportunity missed that still haunts me to this day.

We always had visiting researchers from countries all over the globe. In the early 80’s we had one particular colleague from Poland who was working in a research project and came to our organization to use our advanced computing facilities. At that time the personal computer was still somewhat evolving from its infancy and he did not yet have such machines to use in Poland. Obviously he was quite impressed with the (then rather crude) processing power contained in a small desktop box and immediately started to develop programs for his project on it.

Later in the year it was time for his return to Poland. He decided to purchase a PC to take back with him then found out that the US State Department had placed restrictions on international shipments of PCs and could not take it with him. But after some “creativeness” from our management the PC became classified as “scientific support equipment” and he left a very happy and thankful person.

With respect to your comment regarding reaching retirement age surprisingly quick – aren’t you aware that the speed of time increases exponentially with age? For me at this age simply traveling from the ground floor to the lab in the basement seems to take an hour or two.

Best regards,

Greg


Re: Found Option 7 board DC-508

Miguel Work
 

https://www.ebay.com/itm/Tektronix-DC508-Resolution-Multiplier-and-Option-7-board-DC-508-/153970694486?nma=true&si=XXvWuX%252BQPVnpK2N1t6wWxdBDLlI%253D&orig_cvip=true&nordt=true&rt=nc&_trksid=p2047675.l2557

-----Mensaje original-----
De: TekScopes@groups.io [mailto:TekScopes@groups.io] En nombre de Jean-Paul
Enviado el: sábado, 19 de diciembre de 2020 18:16
Para: TekScopes@groups.io
Asunto: Re: [TekScopes] Found Option 7 board DC-508

nothing on eBay found please give lot number

Jon







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Re: Found Option 7 board DC-508

Siggi
 

Looks like it sold pretty quickly: https://www.ebay.com/itm/153970694486.

On Sat, Dec 19, 2020 at 12:15 PM Jean-Paul <jonpaul@ix.netcom.com> wrote:

nothing on eBay found please give lot number

Jon






Re: 475A Chop Blanking and a Theory Question

Dave Peterson
 

My $0.02 as an IC circuit designer:

We call it parasitic capacitance. But any and all physical implementations of every element of a circuit has parasitic resistance, capacitance, and inductance. Sometimes even parasitic active components. Latchup is when parasitic BJTs in a CMOS circuit get turned on shorting power & ground. Very bad. Can let the magic smoke out. I recall Stanford graduate students doing studies on the effects of parasitic inductance on the clock circuits of Pentium and above class designs. Would Giga-Hertz clocks even work? How would timing be matched and closed across the device? At the time it was not a sure thing at all and it took a fair amount of analysis to understand.

Absolutely the Tek engineers would be accounting for parasitics in the physical design. The legions of engineers coming in to work are largely involved in "back-end" analysis. The design engineering positions are the most sought after coveted positions and usually achieved after serving some time in a back-end role. They account for a relatively small number of the design staff. A large cost of product development is the license fees for the extraction and analysis tools that verify the design after including the physical implementation. In the IC world these are provided by Synopsys and Cadence, FWIW.

My ignorant opinion is that I doubt the orthogonal position of components on a board is considered significant to parasitics. That's not to say all 3 dimensions aren't considered in parasitic analysis, but there is a fair amount of disregarding of "insignificant" parasitics. For example, extraction software has minimum value settings for capacitors and resistors extracted from a physical layout. Resulting network size impacts simulation run time and must be balanced as part of the back-end analysis. The larger the analysis the greater the approximations. Generally, in IC layout, inductance is not extracted at all. To give a sense of how significant disregard is as part of parasitic extraction.

I would not be too concerned about moving the standing position of components too much. To a reasonable extent. I wouldn't go pushing over the vertical series connected resistors, etc. I get why the physical implementation of series resistors distributes the cap more, so would impact frequency response. I wouldn't have thought of that if our more experienced members hadn't brought it up. But I would suspect generally moving components apart is better than otherwise. The designers likely would minimize the impact of parasitic capacitance caused by component proximity. If they needed the capacitance there would be more repeatable means of including it. Field documentation would be explicit about specifying the requirements. I'd think.

But I'm a newb. Just thought I'd chime in on parasitics and how significant they can be, while also disregarded to some extent.

Dave


Re: Found Option 7 board DC-508

Miguel Work
 

I modified my DC508 time ago, I have some photos in photos in our gallery:

https://groups.io/g/TekScopes/album?id=86699




-----Mensaje original-----
De: TekScopes@groups.io [mailto:TekScopes@groups.io] En nombre de Dallas Smith
Enviado el: sábado, 19 de diciembre de 2020 2:05
Para: TekScopes@groups.io
Asunto: [TekScopes] Found Option 7 board DC-508

Hello today,

Hope everyone is doing OK. Found this on Flea-bay - "Tektronix DC508 Resolution Multiplier and Option 7 board DC-508" - for $35 plus S/H. It took me many years to find mine. Just search the quote to find on Flea-bay. I think this is a reasonable deal. Maybe could be used in some other model's? not sure.

Dallas







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Re: So how does this hobby work now?

Michael W. Lynch
 

Excellent Article!
--
Michael Lynch
Dardanelle, AR


Re: So how does this hobby work now?

Tom Phillips
 

Greg,
Thank you for posting the link to the Jim Williams article. I saved many articles written shortly after Jim passed but I had never seen the 5 Years Later article.
Cheers,
Tom


Re: Found Option 7 board DC-508

Jean-Paul
 

nothing on eBay found please give lot number

Jon


Re: 475A Chop Blanking and a Theory Question

Harvey White
 

For the last.... consider the equivalent of stray capacitance to be memory leaks in a memory management system.

Harvey

On 12/19/2020 7:22 AM, Jeff Dutky wrote:
On Sat, Dec 19, 2020 at 02:57 AM, Tom Lee wrote:

You may also find this article by Paul Rako an interesting read: https://www.electronicdesign.com/technologies/analog/article/21807815/whats-all-this-tcoil-stuff-anyhow
Okay, maybe this answers some of the questions I've been having about the 475: is this why they needed the special substrate on the attenuator board, to get a specific stray capacitance?

I've also noticed that components (usually capacitors or transistors) seem to be bent over or away from other nearby components in ways that don't seem merely random, was this part of the factory tweaking? (I really hope not, because I've straightened a few of those on my way through, and I didn't record what I did). You did mention, in the discussion of the series transistors standing on end in the z-axis amp, that the specific arrangement would have resulted in a different capacitance than having the resistors down against the PCB. There are some other arrangements like that in the 475's third pre amp (Q172 and Q182) which I think are C152/L152/R152/R155 and C151/L151/R151/R154, standing vertically off the PCB with the node joining C151/2, L151/2, and R154/5 (I think) soldered together in the air. It's hard to match the board images in the service manual to what I'm seeing in the device, and they don't bother to label every element with silkscreen on the PCB (nor could they have, in this case, as the components are packed too closely together).

I have noticed that necessary stray capacitances are noted in the schematics with grey or dotted elements. This level of detail in the schematics is astonishing to me; I struggle to get all the important details documented in the software I write, and this might be an order of magnitude more complex. Maybe I'm just not aware of it, or maybe I just don't write software with tight enough performance requirements, but I can't think of anything that I deal with that is equivalent to stray capacitance.

-- Jeff Dutky




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