Date   

Re: Yet another use for a curve tracer

Ed Breya
 

The old-fashioned way would work too, but this was simplest for me to turn it on and set up. The whole thing took only a few minutes to check them all. It would take me much longer just to find a bulb socket - I know I should have one somewhere around here.

Ed


Re: Yet another use for a curve tracer

Daveolla
 

Does it not need a minimum load. I just hook them up to the AC cord and a light bulb. I guess I'm stupid for keeping it simple (KISS)

There were opinions earlier on other brand Curve Tracers, EICO and Heath, any opinions from the group on the BK 501A Curve Tracer?

Dave

At 08:18 PM 12/04/2020, you wrote:
I've been cleaning up and organizing lots of stuff lately, and I found I had a couple dozen various AC light dimmers and fan controls piled up. After I eliminated the obvious junkers - marked bad, taken apart, busted parts, etc - I had about a dozen left, to save for possible re-use. I decided to check them out on the curve tracer, to eliminate any more bad ones from stock.

I set up the 576 for AC, 350 V peak range, series R 680 ohms, H 50 V/div, V 100 mA/div, and started testing. It worked great, and all of the two-terminal types checked OK. There are some three- and four-terminal ones that need further study to figure out appropriate hookup. Here's the process, for two-terminal types:

1. Set collector supply to zero.
2. Hook up dimmer.
3 Set collector to about 175 V peak.
4. Run dimmer knob through OFF and full range.
5. Display appearance should change according to dimmer setting, from a flat line or small "+" to a large "+," indicating proper operation.
6. Turn collector back to zero.
7. Disconnect dimmer, and connect the next one.
Repeat as needed.

Ed



Yet another use for a curve tracer

Ed Breya
 

I've been cleaning up and organizing lots of stuff lately, and I found I had a couple dozen various AC light dimmers and fan controls piled up. After I eliminated the obvious junkers - marked bad, taken apart, busted parts, etc - I had about a dozen left, to save for possible re-use. I decided to check them out on the curve tracer, to eliminate any more bad ones from stock.

I set up the 576 for AC, 350 V peak range, series R 680 ohms, H 50 V/div, V 100 mA/div, and started testing. It worked great, and all of the two-terminal types checked OK. There are some three- and four-terminal ones that need further study to figure out appropriate hookup. Here's the process, for two-terminal types:

1. Set collector supply to zero.
2. Hook up dimmer.
3 Set collector to about 175 V peak.
4. Run dimmer knob through OFF and full range.
5. Display appearance should change according to dimmer setting, from a flat line or small "+" to a large "+," indicating proper operation.
6. Turn collector back to zero.
7. Disconnect dimmer, and connect the next one.
Repeat as needed.

Ed


Re: Historical Analog Scope Triggering Techniques

Harvey White
 

analog or digital?

TTL 5 volt levels?

74LS logic ok?

Can you live with a dual polarity supply or do you have only 5 volts available?

Harvey

On 12/4/2020 7:52 PM, Tony Fleming wrote:
Where can I find some schematics that someone like me can follow?
Thanks.

Have a Happy Holidays and wishing you and your family lots of health, love
and no problems!

On Fri, Dec 4, 2020 at 6:42 PM Chris Wilkson via groups.io <cwilkson=
yahoo.com@groups.io> wrote:

On Fri, Dec 4, 2020 at 09:38 AM, Harvey White wrote:
Essentially, I got 8 traces time multiplexed onto 1 trace. Worked for
TTL only, but that's what I needed.
I've done that too. It also works with analog signals. You just need
some analog switches/muxes instead of the TTL digital mux.
In either case, if you run the scope in X/Y mode with the counter driving
"Y" through a DAC you can see all of the traces at once, similar to the
standard "ALT" mode display.

There are a lot of similar tricks you can play by running in X/Y mode with
external helper circuits.








Re: Historical Analog Scope Triggering Techniques

Harvey White
 

I remember trying that, and yes, the restrictions are relaxed.  I think it needs either some extra pins to get the signal out or something that uses the programmer.

I sometimes use extra pins for signal tapoffs, and that's after I've simulated it.  Be aware that the simulator generates *perfect* signals and does very little to simulate a real world input.

Harvey

On 12/4/2020 7:18 PM, Tom Gardner wrote:
On 04/12/20 20:54, Dave Peterson via groups.io wrote:
Caveat: I'm a circuit designer by background. I've been pushing CMOS W&L values around my whole career, so I'm no Verilog/System expert.

However, I am a design engineer at Xilinx and have dabbled a little in our software, Vivado. My understanding is that there is a lot of soft IP that comes included with the SW, including logic analyzers. And when it comes to logic analyzers, I only know that they exist and can guess their purpose and functions to some order. I'll have to take a look at this link above, and this thread gets my head going on possible "projects". For example, they love for us to get to know our products at a user level, and do things like giving us a mini Arduino-like system. Like a Raspberry-PI. I wonder if I can install the above on it. Or look at existing LAs included and see what they can and can't do. But then there's the 23 other "projects" I have going on.

As noted by Tom above: "there is a steep learning curve w.r.t. both the HDL and the toolchain." The system level and toolchain are typically what keep me from getting into this, not the underlying code. Could be fun to bridge the worlds of my past and present.
For Xilinx, the search term is "ChipScope". It is intended to enable you to debug internal nodes in your design, but not much imagination  is necessary to see how it could be used for external nodes.

I've lost track of how to what extent it can be freely inserted in your design, but ISTR they relaxed the requirements a year or so ago.

I presume other manufacturers have a similar "product".





Re: Historical Analog Scope Triggering Techniques

Tony Fleming
 

Where can I find some schematics that someone like me can follow?
Thanks.

Have a Happy Holidays and wishing you and your family lots of health, love
and no problems!

On Fri, Dec 4, 2020 at 6:42 PM Chris Wilkson via groups.io <cwilkson=
yahoo.com@groups.io> wrote:

On Fri, Dec 4, 2020 at 09:38 AM, Harvey White wrote:

Essentially, I got 8 traces time multiplexed onto 1 trace. Worked for
TTL only, but that's what I needed.
I've done that too. It also works with analog signals. You just need
some analog switches/muxes instead of the TTL digital mux.
In either case, if you run the scope in X/Y mode with the counter driving
"Y" through a DAC you can see all of the traces at once, similar to the
standard "ALT" mode display.

There are a lot of similar tricks you can play by running in X/Y mode with
external helper circuits.






Re: Historical Analog Scope Triggering Techniques

Chris Wilkson
 

On Fri, Dec 4, 2020 at 09:38 AM, Harvey White wrote:

Essentially, I got 8 traces time multiplexed onto 1 trace. Worked for
TTL only, but that's what I needed.
I've done that too. It also works with analog signals. You just need some analog switches/muxes instead of the TTL digital mux.
In either case, if you run the scope in X/Y mode with the counter driving "Y" through a DAC you can see all of the traces at once, similar to the standard "ALT" mode display.

There are a lot of similar tricks you can play by running in X/Y mode with external helper circuits.


Re: Historical Analog Scope Triggering Techniques

Tom Gardner
 

On 04/12/20 20:54, Dave Peterson via groups.io wrote:
Caveat: I'm a circuit designer by background. I've been pushing CMOS W&L values around my whole career, so I'm no Verilog/System expert.

However, I am a design engineer at Xilinx and have dabbled a little in our software, Vivado. My understanding is that there is a lot of soft IP that comes included with the SW, including logic analyzers. And when it comes to logic analyzers, I only know that they exist and can guess their purpose and functions to some order. I'll have to take a look at this link above, and this thread gets my head going on possible "projects". For example, they love for us to get to know our products at a user level, and do things like giving us a mini Arduino-like system. Like a Raspberry-PI. I wonder if I can install the above on it. Or look at existing LAs included and see what they can and can't do. But then there's the 23 other "projects" I have going on.

As noted by Tom above: "there is a steep learning curve w.r.t. both the HDL and the toolchain." The system level and toolchain are typically what keep me from getting into this, not the underlying code. Could be fun to bridge the worlds of my past and present.
For Xilinx, the search term is "ChipScope". It is intended to enable you to debug internal nodes in your design, but not much imagination  is necessary to see how it could be used for external nodes.

I've lost track of how to what extent it can be freely inserted in your design, but ISTR they relaxed the requirements a year or so ago.

I presume other manufacturers have a similar "product".


Re: Historical Analog Scope Triggering Techniques

Harvey White
 

I've used Xilinx, the Coolrunner2 (X2Cxxx) CPLD, and Spartan 3AN, and Spartan 6 FPGAS.  I started out in hardware and switched to software, then went over to systems design.

Vivado, unfortunately, will not (as I understand) any of the above chips, you'll need ISE design suite.  The soft ISP available is somewhat limited, and Xilinx (naturally) wants money for this. (That's on the free versions, I can't afford the more expensive ones).

For a logic analyzer, you are likely to need a trigger recognizer (based on the inputs), to start capture.  You'll need an incrementing counter that stores data into the internal memory. The source for this counter can be either an internal clock (derived from a timebase) or an external clock (state machine). I'd suggest an SPI  interfaced register structure (read/write), which requires something like the spartan 6 (it takes space!) to control the system operation.

I've got such, written in VHDL.  I do have eventual plans to build a logic analyzer, running with an ARM processor, color touchscreen display, and battery powered (I have a fondness for portable equipment).  Same processor/interface could easily support a sensor platform and an IC checker.

Most of the problems I've had are to understand the tools, what some of the equivalences there are between the built in (hardware) primitives and the VHDL itself.  VHDL is somewhat a mixture of Pascal, C++, and Basic.  Not too difficult.

There are some nice designs on opencores which can be used, I did find a very nice SPI interface that can be installed with only a few tweaks.

If you're not doing your own PC boards, buying one that has all the bypass caps and as much I/O as possible is a good idea.  If you can get one with a built in programmer (will be needed!), that's a plus.

Again, the major hardware issue, system wise, is the interface levels.  The Xilinx parts that I use are not 5.0 volt tolerant, so that's a problem to solve.  On an individual pin basis, as long as you're doing 3.3 volt only, you can implement the equivalent of a 6820 parallel I/O port.

It's possible to re-engineer some of the Tektronix digital parts using CPLDs or FPGAs (the more the better) for retrofitting, if that's needed.

Harvey

On 12/4/2020 3:54 PM, Dave Peterson via groups.io wrote:
Caveat: I'm a circuit designer by background. I've been pushing CMOS W&L values around my whole career, so I'm no Verilog/System expert.

However, I am a design engineer at Xilinx and have dabbled a little in our software, Vivado. My understanding is that there is a lot of soft IP that comes included with the SW, including logic analyzers. And when it comes to logic analyzers, I only know that they exist and can guess their purpose and functions to some order. I'll have to take a look at this link above, and this thread gets my head going on possible "projects". For example, they love for us to get to know our products at a user level, and do things like giving us a mini Arduino-like system. Like a Raspberry-PI. I wonder if I can install the above on it. Or look at existing LAs included and see what they can and can't do. But then there's the 23 other "projects" I have going on.

As noted by Tom above: "there is a steep learning curve w.r.t. both the HDL and the toolchain." The system level and toolchain are typically what keep me from getting into this, not the underlying code. Could be fun to bridge the worlds of my past and present.

Dave





Re: Peter Keller book payments PayPal won't release

Roy Thistle
 

On Fri, Dec 4, 2020 at 09:54 AM, Tam Hanna wrote:


everyone misunderstands me at the moment.
Tam, I can safely say, I've never really understood your posts; but, I always read, and enjoy, reading them.
I also did offer to help out, here in the colonies.
Best regards.


Re: Historical Analog Scope Triggering Techniques

Tom Lee
 

Anyone who is willing to dive into the innards of a 465 automatically gets a thumbs up in my book.

--Cheers,
Tom

--
Prof. Thomas H. Lee
Allen Ctr., Rm. 205
350 Jane Stanford Way
Stanford University
Stanford, CA 94305-4070
http://www-smirc.stanford.edu

On 12/4/2020 14:08, Dave Peterson via groups.io wrote:
Aw shucks,
Perhaps you should wait to see if I can recover this old 465 before you go talking me up! Wink.
D.




Re: Historical Analog Scope Triggering Techniques

Dave Peterson
 

Aw shucks,
Perhaps you should wait to see if I can recover this old 465 before you go talking me up! Wink.
D.


Re: Historical Analog Scope Triggering Techniques

Tony Fleming
 

I just wish to have your brain Harvey!
Right now I'm learning a new scope made by Micsig, 100MHz, 4 channels,
touchscreen - here is the base model:
https://www.ebay.com/itm/Micsig-STO1104C-Tablet-Oscilloscope-100MHz-4CH-/254666472743?&hash=item3b4b4dfd27-g-8cAAOSwBRdfBef2&autorefresh=true
I've purchased all the updates and battery + the bag - I like to have
everything, so I don't complain later! ha ha ha
But like anything else, it takes time and repetition with my health
problems, so I'll hope to get it sooner than later, ha ha ha
One of the problems is short term memory, so I've developed a system,
probably works just for me, where I just play with the "new toy" and try to
just have fun. After that I take a break, before frustration sets up and
I'll do something else, like writing emails.
Later I'll return - that is the first day. Day 2 is similar, but I try to
achieve something more "interesting", but only if it is fun.... I'm sure
you get the idea. At one point, if I don't forget a small step somewhere, I
can start using what I've learned. Once it's filed in the more permanent
part of my memory, I can find my ways. But if I don't use the "toys" it
reverts back to learning, but the steps are faster - usually.
On the other hand I can remember details about stuff - my friends call it
"useless", like what we did 35+ years ago, when we all learned programming
and other fun stuff.
Sometimes I think my brain has its own preferences now! It remembers what
it's like, not what I want right now to learn. I should follow my own
advice - when I was IT and teach computers or my new employee to assemble a
new PC! - learn only 1-3 items per day, repeat that next few days before
learning something new! We can sometimes teach others the right way, but I
can't listen to myself!
OK, I hope you had enough comedy from above, I'll return to my retired life
and should stop complaining! ha ha ha
Harvey, you have a great weekend and beautiful Holidays!
Tony

On Fri, Dec 4, 2020 at 11:39 AM Harvey White <madyn@dragonworks.info> wrote:

Thank you.

Many years ago, I was working on TTL stuff with a 513D scope. I needed
to look at multiple traces on a somewhat limited scope. I took the
trigger output (I think), reduced it to a TTL pulse per sweep, ran that
to a binary counter, then to an 8 to 1 multiplexer. The output of that
multiplexer drove a common base summer that used the 4,2 and 1 outputs
from the counter as 8,4 and 2 inputs to a homemade (crude!) D/A
converter with the multiplex output going to the 1 input on that A/D.

Essentially, I got 8 traces time multiplexed onto 1 trace. Worked for
TTL only, but that's what I needed.

Harvey


On 12/4/2020 10:58 AM, Tony Fleming wrote:
Harvey I know this isn't the place to thank you for helping everyone,
but I
wish you Happy Holidays and lots of health & love!
And thanks for helping me with my Tektronix scope!!!
I also like to wish you all Happy Holidays and best 2021!
Let's all love each other!
Let's find common ideas and be willing to listen to others!
Tony

On Fri, Dec 4, 2020 at 9:46 AM Harvey White <madyn@dragonworks.info>
wrote:

That or a CPLD, which has less capability and less cost. They're easier
to use if you're making your own boards, but you'll need a programmer,
so additional cost. Remember that while a CPLD has non volatile memory
for the configuration, most FPGAs don't. That should be included on the
development board, and if you're lucky, so will the programmer. Typical
FPGA downloads a pass through program into the FPGA, uses it to program
the memory, then programs the FPGA from the external memory. That
reprogramming is automatic (or can be) when power is applied to the
board.

You'll want to program in either VHDL or Verilog, although I personally
prefer VHDL.

A critical part of the design is that regardless of CPLD or FPGA, the
I/O voltages are ONLY 3.3 volts, and you *must* level translate. There
are chips good for that, though, and you only need one way.

An arduino, touchscreen display, programming, and some sort of interface
to the CPLD/FPGA would set up triggering conditions. Do note that the
FPGA can support a more complex (I2C or SPI) interface, and THAT needs
to be level translated too.

Nice project.

The simpler design would be some dipswitches, 74LS86, 74LS30. One switch
for 1/0, one switch for "don't care". But where'd be the fun in that?

Harvey


On 12/4/2020 9:30 AM, toby@telegraphics.com.au wrote:
On 2020-12-04 2:31 a.m., Jeff Dutky wrote:
Okay, this is all in line with what I've been thinking about: building
a little box that can raise a TTL output on various conditions like a
specific counter bit, or having a 16 bit input value between two
selected
values, or when certain bits are set or cleared, etc. It seems like this
would make all kinds of things visible on a simple analog scope at
relatively little cost (assuming that you don't want to do the
triggering
at clock rates much above a few tens of MHz, of course).
I would consider a tiny FPGA rather than discrete TTL, which would give
you thousands of gates of logic reconfigurable without soldering. You
can get a suitable dev board for ~ $20.


One of the things that I was trying to do with these scopes, before I
got side tracked having to fix them, was to reverse engineer the digital
interface to a gas plasma display in an old laptop. Getting anything
more
than a very general look at the display signals was very challenging,
especially since I didn't understand most of the scope's features very
well, but also because I just wasn't thinking clearly about how to
trigger
the scope and one what. After working on these scopes for the past
month I
think I'm beginning to get a better feel for what they can do and how
they
should be used.
-- Jeff Dutky


















Re: Historical Analog Scope Triggering Techniques

Tom Lee
 

Will do, definitely! I may be meeting him as soon as next week. If I do, I'll be sure to let him know what a valuable employee he has in his group.

--Tom

--
Prof. Thomas H. Lee
Allen Ctr., Rm. 205
350 Jane Stanford Way
Stanford University
Stanford, CA 94305-4070
http://www-smirc.stanford.edu

On 12/4/2020 13:28, Dave Peterson via groups.io wrote:
Yep,
Tell him you ran into me here. He'll get a kick out of it.
Dave




Re: Historical Analog Scope Triggering Techniques

Dave Peterson
 

Yep,
Tell him you ran into me here. He'll get a kick out of it.
Dave


Re: Historical Analog Scope Triggering Techniques

Tom Lee
 

Hi Dave,

Ah, I see , Vamsi's organization. I hope you're having fun!

-- Cheers,
Tom

--
Prof. Thomas H. Lee
Allen Ctr., Rm. 205
350 Jane Stanford Way
Stanford University
Stanford, CA 94305-4070
http://www-smirc.stanford.edu

On 12/4/2020 13:21, Dave Peterson via groups.io wrote:
Hi Tom,

I'm in CAD now. The current organizational name is CPG (Central Products Group). Building Device Model tooling - the stuff that translates the HW into the SW primitives users work with. I started 9 years ago working on various STA activities for the IO team.

Dave




Re: Historical Analog Scope Triggering Techniques

Dave Peterson
 

Hi Tom,

I'm in CAD now. The current organizational name is CPG (Central Products Group). Building Device Model tooling - the stuff that translates the HW into the SW primitives users work with. I started 9 years ago working on various STA activities for the IO team.

Dave


Re: Historical Analog Scope Triggering Techniques

Tom Lee
 

Hi Dave,

Just out of curiosity, for which group at Xilinx do you work?

-- Cheers,
Tom

--
Prof. Thomas H. Lee
Allen Ctr., Rm. 205
350 Jane Stanford Way
Stanford University
Stanford, CA 94305-4070
http://www-smirc.stanford.edu

On 12/4/2020 12:54, Dave Peterson via groups.io wrote:
Caveat: I'm a circuit designer by background. I've been pushing CMOS W&L values around my whole career, so I'm no Verilog/System expert.

However, I am a design engineer at Xilinx and have dabbled a little in our software, Vivado. My understanding is that there is a lot of soft IP that comes included with the SW, including logic analyzers. And when it comes to logic analyzers, I only know that they exist and can guess their purpose and functions to some order. I'll have to take a look at this link above, and this thread gets my head going on possible "projects". For example, they love for us to get to know our products at a user level, and do things like giving us a mini Arduino-like system. Like a Raspberry-PI. I wonder if I can install the above on it. Or look at existing LAs included and see what they can and can't do. But then there's the 23 other "projects" I have going on.

As noted by Tom above: "there is a steep learning curve w.r.t. both the HDL and the toolchain." The system level and toolchain are typically what keep me from getting into this, not the underlying code. Could be fun to bridge the worlds of my past and present.

Dave




Re: Historical Analog Scope Triggering Techniques

Dave Peterson
 

Caveat: I'm a circuit designer by background. I've been pushing CMOS W&L values around my whole career, so I'm no Verilog/System expert.

However, I am a design engineer at Xilinx and have dabbled a little in our software, Vivado. My understanding is that there is a lot of soft IP that comes included with the SW, including logic analyzers. And when it comes to logic analyzers, I only know that they exist and can guess their purpose and functions to some order. I'll have to take a look at this link above, and this thread gets my head going on possible "projects". For example, they love for us to get to know our products at a user level, and do things like giving us a mini Arduino-like system. Like a Raspberry-PI. I wonder if I can install the above on it. Or look at existing LAs included and see what they can and can't do. But then there's the 23 other "projects" I have going on.

As noted by Tom above: "there is a steep learning curve w.r.t. both the HDL and the toolchain." The system level and toolchain are typically what keep me from getting into this, not the underlying code. Could be fun to bridge the worlds of my past and present.

Dave


Re: Historical Analog Scope Triggering Techniques

Mark Litwack
 

There was an FPGA logic analyzer called the "Open Bench Logic Sniffer" that would make a good multi-purpose trigger accessory for a scope by using its trigger out signal. Along with the usual bit matching, it had an advanced mode which had features found in the old HP 16500 series logic analyzer like 10 trigger terms, 2 range terms, 2 timers, and a 16-level state machine. It operated on up to 32 bits of input.

Unfortunately, it's not available anymore, but the schematics, FPGA Verilog code, and host code to control the advanced trigger are all available if someone wanted to use it as a starting point:

http://dangerousprototypes.com/docs/Open_Bench_Logic_Sniffer

The entry under "v3 Demon core in Verilog" has the details on the advanced triggering capabilities.

-mark

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