Re: 475A Chop Blanking and a Theory Question

Dave Peterson

My $0.02 as an IC circuit designer:

We call it parasitic capacitance. But any and all physical implementations of every element of a circuit has parasitic resistance, capacitance, and inductance. Sometimes even parasitic active components. Latchup is when parasitic BJTs in a CMOS circuit get turned on shorting power & ground. Very bad. Can let the magic smoke out. I recall Stanford graduate students doing studies on the effects of parasitic inductance on the clock circuits of Pentium and above class designs. Would Giga-Hertz clocks even work? How would timing be matched and closed across the device? At the time it was not a sure thing at all and it took a fair amount of analysis to understand.

Absolutely the Tek engineers would be accounting for parasitics in the physical design. The legions of engineers coming in to work are largely involved in "back-end" analysis. The design engineering positions are the most sought after coveted positions and usually achieved after serving some time in a back-end role. They account for a relatively small number of the design staff. A large cost of product development is the license fees for the extraction and analysis tools that verify the design after including the physical implementation. In the IC world these are provided by Synopsys and Cadence, FWIW.

My ignorant opinion is that I doubt the orthogonal position of components on a board is considered significant to parasitics. That's not to say all 3 dimensions aren't considered in parasitic analysis, but there is a fair amount of disregarding of "insignificant" parasitics. For example, extraction software has minimum value settings for capacitors and resistors extracted from a physical layout. Resulting network size impacts simulation run time and must be balanced as part of the back-end analysis. The larger the analysis the greater the approximations. Generally, in IC layout, inductance is not extracted at all. To give a sense of how significant disregard is as part of parasitic extraction.

I would not be too concerned about moving the standing position of components too much. To a reasonable extent. I wouldn't go pushing over the vertical series connected resistors, etc. I get why the physical implementation of series resistors distributes the cap more, so would impact frequency response. I wouldn't have thought of that if our more experienced members hadn't brought it up. But I would suspect generally moving components apart is better than otherwise. The designers likely would minimize the impact of parasitic capacitance caused by component proximity. If they needed the capacitance there would be more repeatable means of including it. Field documentation would be explicit about specifying the requirements. I'd think.

But I'm a newb. Just thought I'd chime in on parasitics and how significant they can be, while also disregarded to some extent.


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