Re: Historical Analog Scope Triggering Techniques


Tom Gardner
 

A simulator should show you the timing range of digital signals, which can be experimentally verified with a logic analyser.

For the corresponding analogue waveforms, simulation requires the i/o IBIS models plus a Spice, and verified with an oscilloscope.

On 05/12/20 01:02, Harvey White wrote:
I remember trying that, and yes, the restrictions are relaxed.  I think it needs either some extra pins to get the signal out or something that uses the programmer.

I sometimes use extra pins for signal tapoffs, and that's after I've simulated it.  Be aware that the simulator generates *perfect* signals and does very little to simulate a real world input.

Harvey


On 12/4/2020 7:18 PM, Tom Gardner wrote:
On 04/12/20 20:54, Dave Peterson via groups.io wrote:
Caveat: I'm a circuit designer by background. I've been pushing CMOS W&L values around my whole career, so I'm no Verilog/System expert.

However, I am a design engineer at Xilinx and have dabbled a little in our software, Vivado. My understanding is that there is a lot of soft IP that comes included with the SW, including logic analyzers. And when it comes to logic analyzers, I only know that they exist and can guess their purpose and functions to some order. I'll have to take a look at this link above, and this thread gets my head going on possible "projects". For example, they love for us to get to know our products at a user level, and do things like giving us a mini Arduino-like system. Like a Raspberry-PI. I wonder if I can install the above on it. Or look at existing LAs included and see what they can and can't do. But then there's the 23 other "projects" I have going on.

As noted by Tom above: "there is a steep learning curve w.r.t. both the HDL and the toolchain." The system level and toolchain are typically what keep me from getting into this, not the underlying code. Could be fun to bridge the worlds of my past and present.
For Xilinx, the search term is "ChipScope". It is intended to enable you to debug internal nodes in your design, but not much imagination  is necessary to see how it could be used for external nodes.

I've lost track of how to what extent it can be freely inserted in your design, but ISTR they relaxed the requirements a year or so ago.

I presume other manufacturers have a similar "product".







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