Re: open hardware sampler oscilloscope development video by Ted Yapo mentions Tek many times.


It's a pretty interesting design - and ISTR Ted lays no claim to inventing
it. The low cost comes about because it uses only a DAC and a high-speed
comparator in addition to triggering and timing generation.
It uses equivalent timing samping with successive approximation at a point
in time along the signal. So you feed in a voltage to compare to the signal
at a given time after the trigger, and each sample tells you whether you're
high or low.
Do this N times for an N bit sample - hypothetically.

On Sun, Apr 5, 2020 at 1:47 PM John Griessen <@jgriessen> wrote:

Mentions S-4 sampler, 11801 with SD24's along the way

BOM cost of system he has, (not including various DC supplies), is < $100
for about 7GHz bandwidth.

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