Re: 7S12 with S-4 and S-53 troubleshooting

Nenad Filipovic

I think that offset-feedback loop is not affected by lack of sampling, so
offset control is still functional (just as the input signal were always
zero). Feedback signal enters the head at pins 2&B, and has an
uninterrupted path through gate bias resistors, forward biased D20, D23,
D25 and D28, and Q36. You are correct that offset is balanced in Memory to
keep feedback (actually gate of Q36) constant and ready for integration of
whatever comes from the gate. I was also confused how this circuit deals
with offset being DC, and S-4 preamp not passing DC (C41, C50). Apparently
the pulser baseline offset correction circuit (schematic 15 in the manual)
feeds pulses to the feedback circuit at the head, to which memory also
responds. I did not dive into details of this circuit and I hope I'm not
mistaken, in any case I observed these pulses throughout the whole
preamp-offset-memory-feedback loop, having the snap-off non functional.

I'd also like to hear other members opinions, hope more will join this
discussion after Easter.

Best Regards, Nenad

On Sat, Apr 20, 2019 at 11:30 PM Albert Otten <>

Hi Nenad,

I agree that the avalanche pulse alone is probably so slow that the
clipping lines simply act as a shortcut.
But how to explain the response to the Offset control? When you change
Offset then this change is balanced by an opposite change in Memory voltage
in order the maintain the same voltage at feedback pins 2 & B of the S-4
connector. When the S-4 does nothing then that feedback voltage would
change freely and Memory would not change at all. What is wrong in this


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