Re: 7T11 sampling timebase - how does it behave?


On Wed, May 9, 2018 at 02:47 pm, Dave Wise wrote:

I question one point, Raymond. The 7S14's delay line delays the signal long
enough for the rising edge to hit the sampling gate - not the CRT - after the
trigger. That's what you meant, right?
Yes, Dave, that is sort of what I meant. In my description, I meant to indicate the ultimate goal, which is to show the vertical signal on the crt long enough after the triggering event but maybe I didn't make things as clear as I should have. The delay line has to be positioned *before* the sampling gate i.e. in the analog part, because after the sampling gate the signal isn't an *analog* representation of the input signal anymore nor even a sequence of points of the same edge but a sequence of sampled points on (usually) subsequent edges. So, the analog signal is delayed by the delay lines (one for each channel, DL1 and DL2 in the Service Manual) before being "chopped into pieces". In the SM you can see the "trigger pickoff" (CH1 only) right after the compensation circuits. These serve to compensate for the adverse phase and amplitude effects of the delay line on the signal - and on the input impedance. The trigger signal is output to the horizontal (ramp) circuits on J50.


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