Re: FET leakage question


 

On Fri, 18 Mar 2016 10:13:38 -0500, you wrote:

On 03/17/2016 06:55 PM, Dave [TekScopes] wrote:
There is a trick I have used in the past to make super low leakage
switches using power MOSFETs. If you cascode two of the same MOSFET
in series, then you can bias their midpoint such that one of them
operates with a Vgs of 0 and Vds of 0 when switched off. Under these
conditions, leakage will be minimized.

I would be interested in more detail on this. Are you talking about minimizing Vds leakage of a switch, or Vgs leakage of an
amplifier? Any chance of a schematic?
I was thinking that idea could help my energy harvester boost switcher, but can't figure out
how to bias a pair of transistors as pass transistors to do it yet.

In this schematic, http://ecosensory.com/tek/ecosensory-pv-switcher-1.png
the low leakage pair of enhancement P FET transistors would go in place of Q2

John
When I made this suggestion, I did not know it was a power conversion
application where it does not apply. The bias voltage applied to the
inside of the cascode reduces the leakage of the exposed transistor to
zero but supplies the leakage current to the other transistor. In a
power conversion application where you want to isolate the leakage
back into a source, that does not gain anything because it just
redirects the leakage to ground which has the same effect.

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