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Si5351 current consumption #chat


Eduard Voiculescu
 

A new chat has been created:

Hi guys,

I am comparing the current consumption of the Si5351 under the same conditions (same VCC, same 68 ohm load resistor, full power, unused outputs turned off, steady carrier within the 20m band, same frequency) in two software cases:
 
1. https://www.qrp-labs.com/synth/oe1cgs.html , which looks just about right in terms of power draw to what the U3S is having (~33mA)
 
2. Within the Etherkit 5351 library (https://github.com/etherkit/Si5351Arduino), which you may be also aware of. The instructions are as follows:
 
  si5351.init(SI5351_CRYSTAL_LOAD_0PF, 27000000, 0); - external TCXO
  si5351.drive_strength(SI5351_CLK0, SI5351_DRIVE_8MA); - set max drive for output 0
  si5351.set_freq(1409717000ULL, SI5351_CLK0); - set frequency to 20m;PLL settings are calculated by the library
  si5351.output_enable(SI5351_CLK0, 1); - enable output 0;other are by default turned off
 
This yields about 43mA current draw by the Si5351 (10mA more than U3S/OE1CGS sketch).
 
Adding a couple of instructions to turn off the unused outputs clocks:
 
  si5351.set_clock_pwr(SI5351_CLK1,0);
  si5351.set_clock_pwr(SI5351_CLK2,0);
 
results in a lower current, ~ 39mA, but still about 6mA higher than U3S/OE1CGS sketch.
 
I suspect there is a catch, like finding the exact PLL specifications or turning off the unused PLL or anything like this, but I cannot figure it out. I'm just hoping anyone has any ideas.
 
Thank you,
Eduard YO3ICT

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Shirley Dulcey KE1L
 

Power consumption of CMOS logic depends on operating frequency; the higher the frequency, the more power that is used. CMOS gates use almost no power in either saturated state (on or off), but consume more during transition between the states. Gates cannot switch in zero time; increased frequency means that a larger percentage of time is spent in the non-saturated state, therefore more power.

The two libraries are probably choosing different combinations of PLL and divider settings, with Etherkit going for a higher PLL frequency. That would account for the difference in power consumption that you are seeing, as it would lead to higher power consumption in both the PLL and the dividers.

On Sat, Mar 14, 2020 at 9:48 AM Eduard Voiculescu <yo9ict@...> wrote:

A new chat has been created:

Hi guys,

I am comparing the current consumption of the Si5351 under the same conditions (same VCC, same 68 ohm load resistor, full power, unused outputs turned off, steady carrier within the 20m band, same frequency) in two software cases:
 
1. https://www.qrp-labs.com/synth/oe1cgs.html , which looks just about right in terms of power draw to what the U3S is having (~33mA)
 
2. Within the Etherkit 5351 library (https://github.com/etherkit/Si5351Arduino), which you may be also aware of. The instructions are as follows:
 
  si5351.init(SI5351_CRYSTAL_LOAD_0PF, 27000000, 0); - external TCXO
  si5351.drive_strength(SI5351_CLK0, SI5351_DRIVE_8MA); - set max drive for output 0
  si5351.set_freq(1409717000ULL, SI5351_CLK0); - set frequency to 20m;PLL settings are calculated by the library
  si5351.output_enable(SI5351_CLK0, 1); - enable output 0;other are by default turned off
 
This yields about 43mA current draw by the Si5351 (10mA more than U3S/OE1CGS sketch).
 
Adding a couple of instructions to turn off the unused outputs clocks:
 
  si5351.set_clock_pwr(SI5351_CLK1,0);
  si5351.set_clock_pwr(SI5351_CLK2,0);
 
results in a lower current, ~ 39mA, but still about 6mA higher than U3S/OE1CGS sketch.
 
I suspect there is a catch, like finding the exact PLL specifications or turning off the unused PLL or anything like this, but I cannot figure it out. I'm just hoping anyone has any ideas.
 
Thank you,
Eduard YO3ICT

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Shirley Dulcey KE1L
 

Since the code is open source, you can easily determine the frequencies that the programs are using. Add Serial.print() statements in the appropriate places and look at the results on the serial monitor on your computer. For the version with the Etherkit library you'll have to add them to the library code rather than to your own sketch, but that also comes with source. You'll want to remove those when you put the system in use because they will slow down frequency changes.


On Sat, Mar 14, 2020 at 10:03 AM Shirley Dulcey KE1L via Groups.Io <mark=buttery.org@groups.io> wrote:
Power consumption of CMOS logic depends on operating frequency; the higher the frequency, the more power that is used. CMOS gates use almost no power in either saturated state (on or off), but consume more during transition between the states. Gates cannot switch in zero time; increased frequency means that a larger percentage of time is spent in the non-saturated state, therefore more power.

The two libraries are probably choosing different combinations of PLL and divider settings, with Etherkit going for a higher PLL frequency. That would account for the difference in power consumption that you are seeing, as it would lead to higher power consumption in both the PLL and the dividers.

On Sat, Mar 14, 2020 at 9:48 AM Eduard Voiculescu <yo9ict@...> wrote:

A new chat has been created:

Hi guys,

I am comparing the current consumption of the Si5351 under the same conditions (same VCC, same 68 ohm load resistor, full power, unused outputs turned off, steady carrier within the 20m band, same frequency) in two software cases:
 
1. https://www.qrp-labs.com/synth/oe1cgs.html , which looks just about right in terms of power draw to what the U3S is having (~33mA)
 
2. Within the Etherkit 5351 library (https://github.com/etherkit/Si5351Arduino), which you may be also aware of. The instructions are as follows:
 
  si5351.init(SI5351_CRYSTAL_LOAD_0PF, 27000000, 0); - external TCXO
  si5351.drive_strength(SI5351_CLK0, SI5351_DRIVE_8MA); - set max drive for output 0
  si5351.set_freq(1409717000ULL, SI5351_CLK0); - set frequency to 20m;PLL settings are calculated by the library
  si5351.output_enable(SI5351_CLK0, 1); - enable output 0;other are by default turned off
 
This yields about 43mA current draw by the Si5351 (10mA more than U3S/OE1CGS sketch).
 
Adding a couple of instructions to turn off the unused outputs clocks:
 
  si5351.set_clock_pwr(SI5351_CLK1,0);
  si5351.set_clock_pwr(SI5351_CLK2,0);
 
results in a lower current, ~ 39mA, but still about 6mA higher than U3S/OE1CGS sketch.
 
I suspect there is a catch, like finding the exact PLL specifications or turning off the unused PLL or anything like this, but I cannot figure it out. I'm just hoping anyone has any ideas.
 
Thank you,
Eduard YO3ICT

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Mike
 

Eduard,

This is an interesting observation. I have beacons on the air using the Arduino and SI5351A and am interested in trying to duplicate your test.
I have some questions regarding your test setup;

Where in your circuit did you place the current meter?
Did you use the same Arduino in each test?
Did you use the same SI5351A chip/circut/level converters?
Did you use the same meter in each test?

Thanks in advance for the extra info.
Mike N8OOU


Eduard Voiculescu
 

Everything is the same. Same board, same meter, same Si5351, same VCC, same load.

The current meter is placed right on the board supply. Its a custom board. Its only a matter of the firmware.

Need to investigate what KE1L suggested.


Mike
 

Eduard,

OK, on the setup, but just one thing I am not clear on. You say the metering is on the supply to your custom board, What functions are on that board?
Amtel uP, level converters,SI5351A?
I want to make sure I meter the same components.

Yes I agree that KE1L suggestions need investigated. Especially in the area of I2C level conversion/communications. The SI5351 can be set up with just a few register transfers, or a continuous stream of redundant commands that just waste energy. Those redundant commands can cause havoc on the SI output signal.

Mike N8OOU


Eduard Voiculescu
 

Mike,

Do not mind about the board.

Additional functions/devices are into sleep mode or disabled completely. If you can do this measurement, stick with relative measurements between the 2 firmwares.

Shirley,

You are right.

Manually downgrading the Etherkit implementation's PLL frequency to the minimum allowed (600MHz) saves another 2mA. This is done with a simple command :
si5351.set_freq_manual(1409717000ULL, 60000000000ULL, SI5351_CLK0);

But after doing the math, the OE1CGS sketch reveals that it sets the PLL frequency much higher, at ~874MHz, while consuming less power.

I'm puzzled.


Hans Summers
 

Hi Eduard

Another idea to check. 

There are two ways to set up the Si5351A. 

1) use a fractional feedback divider on the PLL. Then even integer for the MultiSynth. This is the method recommended by the Si documentation (and common sense intuition) for lowest jitter i.e. best phase noise performance. Furthermore this method has other advantages such as allowing the quadrature output mode used in QCX. All QRP Labs products use this way. 

2) use a fixed integer feedback on the PLL and a fractional MultiSynth divider. This is the method used by the Si5351A Linux driver that the Etherkits library was originally ported from. I'm not sure if this has been changed since then. Last time I looked at the Etherkits library it did this method 2. But I haven't looked at it for a few years and I'm sure it was improved over time. 

If one sketch is using method 1 (which I believe is by far the superior way) and the other is using method 2, it may be that this could be a factor on current consumption. I think Si do some tricks to reduce the phase noise impact of a fractional MultiSynth divider and perhaps these tricks consume some mA. There is even an "even integer MS divider" bit on the clock configuration registers. That could switch out the MS fractional MultiSynth divider cleanup stuff. 

73 Hans G0UPL 


On Sat, Mar 14, 2020, 18:27 Eduard Voiculescu <yo9ict@...> wrote:
Mike,

Do not mind about the board.

Additional functions/devices are into sleep mode or disabled completely. If you can do this measurement, stick with relative measurements between the 2 firmwares.

Shirley,

You are right.

Manually downgrading the Etherkit implementation's PLL frequency to the minimum allowed (600MHz) saves another 2mA. This is done with a simple command :
si5351.set_freq_manual(1409717000ULL, 60000000000ULL, SI5351_CLK0);

But after doing the math, the OE1CGS sketch reveals that it sets the PLL frequency much higher, at ~874MHz, while consuming less power.

I'm puzzled.


Mike
 

Eduard,

I did a test of three different firmwares and measured the current consumption. I used the same meter, same hardware, the only change was the Arduino sketch. I don't think giving my exact mA numbers would mean anything given a 10 to 15 % tolerance on components and meters, I will state that the Oscillator sketch measured at about half of the current used by the eitherkit sketch. That difference was 22 mA which to me seems like a lot. My personally developed beacon sketch was a 4 mA more than the Oscillator sketch, but that is apples/oranges because the beacon is changing frequency compared to the constant frequency of the other two sketches.

With this simple test I conclude that the firmware logic can have a significant impact on the power consumed by the SI5351A, and the 5v to 3.3v level shifting circuitry. I did not attempt to measure current flow in those two components.

An interesting, but understandable, measurement was that the base Arduino, without any additional hardware consumed the same current with all three firmwares.

I don't know that these results explains the root cause, but I think it confirms your observations.

Mike N8OOU