Date   

Re: Kit shipping

n4qa at_hotmail.com
 

OOPS!
That one paragraph should has started "So, anyway, fast forward to Spring 2019." not 2017...
ahem...

72 / 73,
Bill, N4QA


Re: Kit shipping

n4qa at_hotmail.com
 

You think that *you guys* have a shipping story !
 
I ordered one each QCX-80 & QCX-17 back around the autumn of 2017.
At that time, they were kitted in Japan.
As I recall, delivery time was about three weeks.
 
I dragged my feet for several weeks after delivery...
After a heart attack and a stroke, followed by triple bypass surgery, the 'Small Packet' from Japan sat, unopened, on a workbench for a year and a half...
But, don't worry, I'm back in great shape now !
 
eh? What's that, Dear? Oh, please excuse me for a few moments, fellas...
 
The wife had me join her to finishing watching 'Just like Heaven', starring Reese Witherspoon and Mark Ruffalo...nice flick !
Ok, I'm back.
 
Martha asked me in '17 if I'd let her keep those Japanese stamps..."Of course", I replied.
 
So, anyway, fast forward to Spring 2017.
I met my new ham friend, Bill, AF4YF from Patrick County, Virginia on 80 CW a few months ago.
Soon thereafter, Bill & I had lunch together and I invited him to our home to see my stuff...
At some point, I said to Bill "Have I got a deal for you !".
So, I told Bill that the QCX-80 kit was his, provided that he would build the QCX-17 for me.
He agreed!
 
Oh, yeah, a couple of months ago, I ordered an assembled QCX-80 from Hans' outfit in Turkey.
That order also took a couple of weeks to arrive...WELL worth the wait!
Once again, Martha gets the stamps, this time, from Turkey.
 
And, the rest, as they say, is history !
 
72 / 73,
Bill, N4QA


Re: U3S - xmit frequency is 200 Hz higher than indicated on display

Klaus Beckers
 

Hi John
  This is Klaus, DL2QB (also WN2Z). I am not sure if I fully understand your question. Just connecting the U3S with a GPS and then doing nothing more won't guarantee that the U3S is working on the proper frequency indicated by the display. Unlike the procedure with e.g. the QCX QRP tfansceiver where you onxe set the proper osciallting frequncy in the beginning and leave the QCX alone more or less, on the U3S you must set up the correcting frequncy calibration after every cycle of WSPR transmissions- So you should specify how often and too what degree the U3S is commanded to compare the frequency of your master oscillator (not the one that controls the clock for the processor) with the standard it has just received   (pps pulses) from the GPS unit. You can specify in what steps and how often your oscillator has to be compared with the GPS standard and after that has been done, the U3S will correct the U3S oscillating frequency accordingly. After such a correcting cycle you will see a short message on the display that says -003 or +015 or 000 which will tell you how many Hertz (Hz) the frequency has been corrected. If you have your U3S close to a window pane you can easily see the drift of the xtal oscialltor due to the change in environmental temperature. If you don't set up this calibration cycle like described in the U3S manual, the xtal oscillator may drift so far that the final transmitting frequency is off -and in worst case- outside the WSPR band. My aplogies if I have not always found the proper wording, English ist not my mother language and may be I also did not fully understand your problem.

73 from Cologne
Klaus
DL2QB


U3S - xmit frequency is 200 Hz higher than indicated on display

John Canfield <bucket@...>
 

First off, my apologies if this has been answered/discussed/in the manual. Some kind soul emailed me saying I was transmitting 100Hz outside of the WSPR frequency range on 30M, I always thought I didn't get very many reports due to my antenna, etc. I dropped my xmit frequency by 100Hz which put me right at the top of the WSPR range and started getting a bunch of reports. I dropped the frequency another 100 Hz (200 Hz in total) which put me right in the middle of 30M WSPR. Now I'm getting >= 20 spots every hour.

This U3S has a GPS that is successfully talking to the U3S and I was under the impression that with the attached GPS, there was no need to fiddle with the oscillator frequency. I could lower the oscillator frequency by 200 Hz but then what's the point of having the attached GPS? What don't I understand here? Again - sorry if this is a dumb question.
--
John, WB5THT


Re: Kit shipping

N3MNT
 

On my orders, once they left Turkey there was a period of tracking silence until the reached  customs.


Re: Kit shipping

Jim - W7EZN
 

I live in western Oregon (Eugene) and shipping takes about 18 days.   The product is well worth the patience...:)
--
Jim, KJ7EZN    73!


Re: Kit shipping

Mike Strelitzer <mstrelitzer@...>
 

I'm in SE Wisconsin, near Milwaukee, and mine took 17 days, if I remember correctly. Just a frame of reference for those wondering.
73
Mike

On Sun, Apr 14, 2019, 10:46 AM Bill Cromwell <wrcromwell@...> wrote:
Hi,

I have a couple of kits coming here in the Great Lakes region USA. I see
the kits left Turkey a while back and nothing beyond that. I just have
to wait. Not everything carries "instant gratification". It took me 72
years to order the kits. A few more days one way or the other will not
matter at all.

73,

Bill  KU8H

On 4/14/19 10:43 AM, Hans Summers wrote:
> Yes unfortunately standard international package tracking in UK isn't
> very good compared to nearly every other country. But the packages will
> still arrive just fine, be patient for them sometimes!
>
> 73 Hans G0UPL
> http://qrp-labs.com
>
> On Sun, Apr 14, 2019, 17:34 geoff M0ORE via Groups.Io
> <m0ore=tiscali.co.uk@groups.io <mailto:tiscali.co.uk@groups.io>> wrote:
>
>     Hi Dennis,
>
>     Don't know which part of the world you are in but looking at your
>     time of posting, I think you maybe a few degrees east of Turkey.
>
>     Here in the UK, the kits I have purchased show item leaving Turkey
>     and then arriving at UK customs at the Royal Mail warehouse at
>     Heathrow then nothing until the package drops through the letter
>     box. This can take several days just in the UK.
>
>     On 14/04/2019 14:41, Hans Summers wrote:
>>     Hi Dennis
>>
>>     The tracking will (in most countries) also be updated in the
>>     destination country, once it clears customs. There can be a
>>     variable delay for that to happen. See also the information on
>>     http://qrp-labs.com/shipping and http://qrp-labs.com/faq#stuck
>>
>>     73 Hans G0UPL
>>     http://qrp-labs.com
>>
>>     On Sun, Apr 14, 2019, 16:31 dkwflight <dkwflight@...
>>     <mailto:dkwflight@...>> wrote:
>>
>>         The tracking number only shows the status in Turkey.
>>         It showed the kit was forwarded to the destination country on
>>         April 10.  I have to be patient.
>>         Thanks
>>         Dennis
>>
>

--
bark less - wag more




Re: Kit shipping

Bill Cromwell
 

Hi,

I have a couple of kits coming here in the Great Lakes region USA. I see the kits left Turkey a while back and nothing beyond that. I just have to wait. Not everything carries "instant gratification". It took me 72 years to order the kits. A few more days one way or the other will not matter at all.

73,

Bill KU8H

On 4/14/19 10:43 AM, Hans Summers wrote:
Yes unfortunately standard international package tracking in UK isn't very good compared to nearly every other country. But the packages will still arrive just fine, be patient for them sometimes!
73 Hans G0UPL
http://qrp-labs.com
On Sun, Apr 14, 2019, 17:34 geoff M0ORE via Groups.Io <m0ore=tiscali.co.uk@groups.io <mailto:tiscali.co.uk@groups.io>> wrote:
Hi Dennis,
Don't know which part of the world you are in but looking at your
time of posting, I think you maybe a few degrees east of Turkey.
Here in the UK, the kits I have purchased show item leaving Turkey
and then arriving at UK customs at the Royal Mail warehouse at
Heathrow then nothing until the package drops through the letter
box. This can take several days just in the UK.
On 14/04/2019 14:41, Hans Summers wrote:
Hi Dennis

The tracking will (in most countries) also be updated in the
destination country, once it clears customs. There can be a
variable delay for that to happen. See also the information on
http://qrp-labs.com/shipping and http://qrp-labs.com/faq#stuck

73 Hans G0UPL
http://qrp-labs.com

On Sun, Apr 14, 2019, 16:31 dkwflight <dkwflight@hotmail.com
<mailto:dkwflight@hotmail.com>> wrote:

The tracking number only shows the status in Turkey.
It showed the kit was forwarded to the destination country on
April 10.  I have to be patient.
Thanks
Dennis
--
bark less - wag more


YAY ! Finally had my first 17m CW Q using the totally stock QCX-17 !

n4qa at_hotmail.com
 

Decided to tune around the 17m band to see what I might fine.
There was XE2V calling CQ on 18082 kHz.
Had a quick Q with om Mode after which he worked a bunch of others.
QCX-17 finals nice & cool at 2.5 watts out to the GADS! antenna.
OK, back to 15 meters...

72 / 73,
Bill, N4QA


Re: Kit shipping

Hans Summers
 

Yes unfortunately standard international package tracking in UK isn't very good compared to nearly every other country. But the packages will still arrive just fine, be patient for them sometimes!

73 Hans G0UPL 

On Sun, Apr 14, 2019, 17:34 geoff M0ORE via Groups.Io <m0ore=tiscali.co.uk@groups.io> wrote:

Hi Dennis,

Don't know which part of the world you are in but looking at your time of posting, I think you maybe a few degrees east of Turkey.

Here in the UK, the kits I have purchased show item leaving Turkey and then arriving at UK customs at the Royal Mail  warehouse at Heathrow then nothing until the package drops through the letter box. This can take several days just in the UK.

On 14/04/2019 14:41, Hans Summers wrote:
Hi Dennis

The tracking will (in most countries) also be updated in the destination country, once it clears customs. There can be a variable delay for that to happen. See also the information on http://qrp-labs.com/shipping and http://qrp-labs.com/faq#stuck

73 Hans G0UPL 

On Sun, Apr 14, 2019, 16:31 dkwflight <dkwflight@...> wrote:
The tracking number only shows the status in Turkey.
It showed the kit was forwarded to the destination country on April 10.  I have to be patient.
Thanks
Dennis


Re: Kit shipping

geoff M0ORE
 

Hi Dennis,

Don't know which part of the world you are in but looking at your time of posting, I think you maybe a few degrees east of Turkey.

Here in the UK, the kits I have purchased show item leaving Turkey and then arriving at UK customs at the Royal Mail  warehouse at Heathrow then nothing until the package drops through the letter box. This can take several days just in the UK.

On 14/04/2019 14:41, Hans Summers wrote:
Hi Dennis

The tracking will (in most countries) also be updated in the destination country, once it clears customs. There can be a variable delay for that to happen. See also the information on http://qrp-labs.com/shipping and http://qrp-labs.com/faq#stuck

73 Hans G0UPL 

On Sun, Apr 14, 2019, 16:31 dkwflight <dkwflight@...> wrote:
The tracking number only shows the status in Turkey.
It showed the kit was forwarded to the destination country on April 10.  I have to be patient.
Thanks
Dennis


Re: A somewhat more complete description of my (ab)use of the QCX-17 and QCX-80 transceivers

n4qa at_hotmail.com
 

Probably more than you ever wanted to know about an overworked QCX-17...


With appropriate external filter ( except, none for 17m )
 
OHR WM-2 QRP Wattmeter Bird model 10-A-MFB-30 attenuator as a dummy load
 
3.9 Band = as per band of operation
 
 
QCX-17 power output estimated erp GADS! antenna ( GADS! = Gutter And Down Spout! )
 
3501.7 kHz  500 milliwatts 60 milliwatts
 
5332 kHz    1 watt        250 milliwatts
 
7001.7 kHz  1 watt        500 milliwatts
 
10101.7 kHz 4 watts 3 watts
 
14001.7 kHz 4 watts 4 watts
 
18069.7 kHz 2.5 watts  2.5 watts
 
21001.7 kHz 1.5 watts 1.5 watts


Yes, there's that thing about class E amps.
But, have a look at my RBN spots for the current 'RBN week' - all spots of the QCX-17 with appropriate external output filter.

Have also made a few actual QSOs using the stock QCX-17 on 30 & 20m. None yet on 17 due to poor condx.
QCX-17 works well on 15m too but spots are hard to come by on 15 due, again to poor condx.
When operating on any band, I keep a couple of fingertips on the finals to get a 'sense' of how they're doing.
I've been too lazy so far to put a 'scope on the drains of Q1, Q2, Q3 but, I'm pretty sure I'd see them coming out of saturation :0)
 
The QCX-80, with its built-in 80m lpf isn't nearly as frequency-agile as the -17 is for obvious reasons...unless we decide to rearrange things a bit.
 
Oh yeah, my -17 is now a 7-band rig ! Only manages about 500 milliwatts out on 80 but, sometimes, that's enough.
80, 60, 40, 30, 20, 17, 15m...plus CHU 3330, 7850, 14670, and WWV / WWVH 5000, 10000, 15000...haven't yet heard WWV on 20000 kHz...matter of time and condx.
Oodles & boodles of broadcast stations too.

Any questions ?
 
72 / 73,
Bill, N4QA


Re: Kit shipping

Hans Summers
 

Hi Dennis

The tracking will (in most countries) also be updated in the destination country, once it clears customs. There can be a variable delay for that to happen. See also the information on http://qrp-labs.com/shipping and http://qrp-labs.com/faq#stuck

73 Hans G0UPL 

On Sun, Apr 14, 2019, 16:31 dkwflight <dkwflight@...> wrote:
The tracking number only shows the status in Turkey.
It showed the kit was forwarded to the destination country on April 10.  I have to be patient.
Thanks
Dennis


Kit shipping

dkwflight
 

The tracking number only shows the status in Turkey.
It showed the kit was forwarded to the destination country on April 10.  I have to be patient.
Thanks
Dennis


Re: SDR Reveivers?

John VA7JBE
 

Thanks everybody!

Richard, the Quadnet keyword was enough to help me find the software (which is super useful) and also several other projects by people who've built analog all pass filters of varying complexity.  These, along with the Quadnet software, have been very helpful as I try to get my head around this.  With careful component selection, some of these designs are claiming better than 70dB of opposite sideband suppression!  For reference, here they are:

W6JL's 10 pole phasing receiver
http://cbjohn.com/aa0zz/PPLLUsers/W6JL/W6JL.pdf

YU1LM's 8 pole phasing transceiver
http://yu1lm.qrpradio.com/AF%20ALL-PASS%20NETWORK-YU1LM.pdf

WA5BDU's 6 pole receiver, adapted from EMRFD (PowerPoint)
http://pages.suddenlink.net/wa5bdu/phasing_rx_wa5bdu.pptx

The Scientist and Engineers Guide to DSP is a resource I've stumbled across before, but thanks to Geoff for refreshing my memory!  There's definitely some good reading in there, and it looks like I'll have to finally go find a copy of EMRFD to call my own.  I had wondered if it would be possible to put together a simple monoband SSB rig patterned after the QCX, but for sideband.  From what I've found today it looks possible, though I'm still not sure how to get 45dB of sideband rejection out of a third order all pass filter.  i suppose I'll have to read on to find out!

Cheers,

John VA7JBE


Re: Fried U3s on 12volts. Hopeless? #u3s

 


Just completed mods to U3s and mistakenly applied 12v supply to 5 v bus. Pinned the ammeter, hard.
Replaced synthesizer and eprom.  QLG1 GPS not flashing.
Only thing not replaced is the display board.  Shows   most signs of life but won't tx.
Any hope of recovery?  What components likely damaged?  Maybe start with a new U3s?
Tom
It has been done before http://qrp-labs.com/faq.html#fry

Tom:

Did you ever get your  U3 going?  


--
73, Bernie, VE3FWF


Re: Qrp-labs and a Huff and Puff circuit board

Joe Street
 

Thanks Arv

Yeah I am not a newcomer to PIC programming so it is even more embarassing.  The Norcal 2030 that I want to use this on mixes the 3MHz PTO with a crystal to get the final operating frequency and there is a varactor on the VXO side for RIT and another one for the Rx/Tx offset and uses an anoalog mux to switch voltages over there so I don't have to worry about dealing with RIT etc on the PTO.  I suspect others may want a design that plays nice with RIT so the counter based huff & puff is probably the one they want. That design is here:   https://www.qsl.net/om3cph/counter/lcd/contribs/pic_flck.htm  The NC2030 also has a frequency counter already that announces via CW so it doesn't need another one.

Now to see if I can leverage the nanowatt technology of the PIC18 and make this thing run on minimal power.

J


On Sat, Apr 13, 2019 at 7:09 PM Arv Evans <arvid.evans@...> wrote:
Joe

Congratulations.  Sounds like you are well on the way to becoming more stable...!
The start at zero versus start at 1 is a very common error.  Even the experts do
that frequently.  We count by ones, but computers do it with zeros and non-zeros.

Once you have all this worked out I suspect that there will be some interest by others
to use you design for tube-type rigs, and for solid state analog VFO units. 

Arv
_._


On Sat, Apr 13, 2019 at 4:23 PM Joe Street <racingtheclouds@...> wrote:
Hold the phone Arv!  On a hunch I thought what if the way the shift register is being handled is messed up somehow, and sure enough it was.  In porting the code to the new architecture I defined a length variable and added it to the start address of the array when I should have added (length -1).  Duh.  A real newby error.  So it was XOR'ing the current logic state with a fixed bit from memory.  No wonder it was mostly unresponsive except at specific frequencies (probably harmonically related to the processor clock).  Now that I have fixed that I get the expected behaviour, and every 5 hz the integrated output changes direction (increasing vs decreasing) repeating the cycle every 10Hz.  YAY!  What an elegant design.  Now to build the VFO and get on with that part.

Joe

On Sat, Apr 13, 2019 at 5:12 PM Arv Evans <arvid.evans@...> wrote:
Joe

I may not be of much help here.  I was assuming that your design was a traditional H&P
layout.  You did express yourself well, I just did not read it well. 

The G4DXZ design is PIC based with most of the heavy lifting being done inside the
micro-processor itself.  This gets involved with Nyquist speed in both hardware and software. 
Several years back Ian K3IMW did send me a PIC with the G3DXF stabilizer software installed.
It worked so well that I did not really get involved with the how or why it did so. 

Arv
_._


On Sat, Apr 13, 2019 at 2:42 PM Joe Street <racingtheclouds@...> wrote:
Hi Arv

I think I didn't express it well.  All the functionality is internal to the microprocessor except for an RC integrator on the output pin.  So a timer is setup to generate a hardware interrupt at the chosen sample rate (2929.6hz in this case).  In the interrupt service routine the logic state at the frequency input pin is sampled and it is either logic high or low at that instant. The logic state is saved and shifted into a memory based delay line or shift register in this case with 296 stages and all the bits get shifted once per sample period.  The last thing the service routine does is compare the current logic state to the last bit in the shift register after shifting and do an exclusive or. Then the processor simply loops doing nothing till the next timer interrupt.  The logical output of the XOR is a toggling bit stream sent to the output port pin and yes it is either high or low but if you filter it with a long timebase RC you get a DC value proportional to the duty cycle of that output bit.  What I am finding is that close to certain frequencies the duty cycle changes rapidly with a very small shift in input frequency. This I take it is the action which causes frequency lock as the filtered output is supposed to ultimately drive a varactor in the VFO.  If I deviate the input frequency below said frequency the duty cycle goes toward 0% which integrates to a DC value near ground and if I deviate the input frequency a little above said frequency then the duty cycle tends toward 100% which gives a DC level near Vcc which would increase capacitance in the varactor and drive the frequency back down.  However outside of this small input frequency range the duty cycle tends to be close to 50% for a broad range of input frequencies which means the integrator output sits near Vcc/2.  When I read about this technique I imagined that since the code is designed to create a 10 hz lock step I should see the duty cycle range between its high and low extent in a cyclical way every 10Hz as I vary the input frequecy, but it is not the case.  Imagine I start to increase the input frequency till the DC level gets to Vcc (tries to drive the VFO back down) but if I keep going shouldn't the duty cycle suddenly flip at some point causing the integrated DC to drive low and thus reducing the varactor capacitance and thereby driving the VFO frequency UP to the next lock point?  I know I am testing this thing open loop but if it is going to work the way it is described, shouldn't I see the behaviour I just described repeating every 10Hz as I sweep the input frequency?

Here is the paper I am working from which describes the code I downloaded.  http://www.hanssummers.com/images/stories/library/ttjun07.pdf

Joe

On Sat, Apr 13, 2019 at 2:23 PM Arv Evans <arvid.evans@...> wrote:
Joe

Output of the leading/lagging slicer should be either high or low...no in-between state.
I would start troubleshooting that area. 

If using a D-type FF for the comparison function...its outputs can only be high or low.  There
is no analog output in these circuits.  On a slow scope or voltmeter the output can appear
to be vcc/2 if it is changing rapidly enough to be averaging in the test instrument.
If the VFO input is always higher than the reference transition the D-type FF output should
always be one polarity, depending on which output you use.  If always lower then the polarity
should always be the same but opposite polarity.


Arv
_._


On Sat, Apr 13, 2019 at 12:07 PM Joe Street <racingtheclouds@...> wrote:
Thanks Arv

Yeah it is a very curious thing.  I am injecting a TTL level signal from a DDS for testing so the input level is not a factor.  What gives me doubts about continuing with this design is what is going on when there is not an obvious response action on the control output.  When the action is obvious it makes sense ie as I vary the input frequency up/dn the control output duty cycle varies from 100% to 0% and the integrated output creates a DC swing virtually rail to rail but there are also spots where the integrated output shows only a small swing around vcc/2.  Now on the scope as I vary the input up/dn I see there is definitely a point at a certain frequency where the variation in duty cycle slows and the integrated signal transitions from a sine wave to DC but the amplitude of the swing is small and therefore would have a much less powerful affect on the varactor.  Is that considered a lock point?  If you look at the digital output before the integrator you only see a square wave, the variations in the duty cycle are so small you don't notice them on the scope but you see the effect once integrated.  How this would play if I closed the loop around an actual VFO instead of testing the way I am isn't intuitively obvious.  I am tempted to put this one aside and try the one with the frequency counter which I suspect may require less black arts skills!

Joe

On Sat, Apr 13, 2019 at 1:39 PM Arv Evans <arvid.evans@...> wrote:
Joe

I have to admit that when Hans first brought H&P to my attention several years ago it took
me several months before I was forced to admit that it was not a mixer.  Key concept  is edge
alignment between the two signals (VFO and reference clock).  Once I had set aside my
own attempt to do an Arduino version and built a simple D-type FF based version, things
began to make more sense to my feeble brain. 

My first working H&P used a 32 Hz reference from a divider on a 32 KHz crystal oscillator,
with a 74HC74 as comparator and things started to work better.  From there it was just a matter
of fine tuning levels to make it actually control the VFO side of things.  Note, there is no
"lock" state in H&P.  It always slowly wanders up and down about 1 Hz around multiples
of the reference clock.  Time delay in the control loop and coupling between the varactor
and oscillator tank make its action more aggressive or less aggressive.  If too aggressive the 
frequency control will feel "sticky".  Inadequately aggressive circuits may jump tuning steps
if the VFO drift rate exceeds frequency correction rate. 

My second working version had way too much control of the VFO and refused to tune in
desired steps.  It would hold a set frequency until I had tuned the VFO several steps away
from the 32 Hz reference and then jump several steps to the nearest 32 Hz based reference
point.  After I added a series resistor in the feedback loop this build settled down and is still
being used to stabilize an old BITX40A. 

There are several ways to implement H&P.  My versions used a D-type FF to latch HIGH or LOW
based on edge comparison between the LF reference and the VFO.  Just to prove a point I did
build one that reversed the HF and LF parts by dividing the VFO down to LF and comparing that
with a HF reference clock.  That works maybe better for my friends in Australia and New Zealand
where things are normally upside down.   8-)

Other versions of H&P are set up to always push or pull the frequency in one direction, with drift
compensation adjusted to always drift in the opposite direction.  That just confused me so I
mostly avoided this idea.

It should be possible to use some sort of discrete component multi-vibrator circuit to replace
the comparison latch.  This might be a valid approach for tube-type VFOs where the voltages
are higher than nominally 5V TTL levels.  I did model this in LTSpice but never actually built one. 

H&P is sensitive to signal levels because this affects the point where the latch (D-type FF)
senses leading or lagging conditions and toggles its output accordingly.  Adding a Schmidt-trigger
CMOS gate(s) ahead of the latch  inputs could minimize this and might reduce any jitter output
from the phase comparison action.

All of the several H&P circuits that I have built required some fine-tuning before they would
work properly.  This adds credibility to Hans` statement about H&P probably not being
something that could be offered as a kit that others could just plug into existing circuits and
expect it to work first try. 

I did go back to an Arduino based FLL (not H&P) design that counts VFO frequency and
compares that with a user-entered frequency value.  This is an easier thing to get working
and it does have 3-states (too high, locked, and too low).  This does not have set tuning steps
unless you design that into the software side of things.  Tuning rate can be made variable
based on how far off-frequency the measured VFO might be.  Some may disagree but this
seems closer to an FLL than a traditional H&P design. 

There are micro-controller based stabilizers that claim to be H&P but I have never seriously
tried to use or duplicate them. 

Don't know if any of this is helpful.  H&P is an interesting concept, and one that can be
implemented successfully if time is taken to fully understand how it works and to fine-tune
the circuitry.

Arv
_._

On Sat, Apr 13, 2019 at 9:48 AM Joe Street <racingtheclouds@...> wrote:
Well last night I had a bit of a play around with the software type shift register and XOR implementation using a Sparkfun UBW board which has a PIC18 processor and a 24MHz crystal.  G3DXZ originally ran this on a PIC16 architecture with a much lower frequency crystal to get a 5Hz lock step, but I used an internal prescaler to get a very close RF sample rate of 2929.6 Hz and a shift register size of 296 bits (37 bytes) so this, according to the lore, should result in a lock step size of 2929.6 / 296 = 9.89 Hz which is as close as I could get to 10hz with this particular crystal and approach.  If I modified the code I could reduce the shift reg to 293 bits and get 9.998Hz but it is written to use a shift register which is a full multiple of 8 bits so I stuck with that and went ahead and did some testing.  Ironically today I can feed a test signal from a DDS source with high stability and adjust the frequency in 0.01Hz steps and observe the control output with the system open loop.  I used an integrator of 390Kohm feeding a 1uF on the output.  What I saw on the scope was fascinating but unfortunately I'm still a little perplexed about how this technique works!  What I observed was that the integrated output produces a heterodyne, the frequency of which is highly responsive to the exact frequency at the input and increases in amplitude as the heterodyne approaches 0 Hz.  However, I expected this behaviour to be cyclical and repeat at intervals of 9.9hz, which it did not.  It is difficult to find these lock points as they are extremely sensitive to very small changes in frequency at the input and the amplitude of the observed heterodyne diminishes rapidly as its frequency departs from DC either side and this happens within a few 0.01hz steps change of input frequency up or down from the DC output point!  So scanning the input frequency in 1 hz steps, you easily miss a strong response on the control output. At first I didn't think it was working at all and that there was a mistake in porting the code to the new architecture, but then I realized I needed to vary the input frequency much more slowly than I was.  This was fascinating and I played around for a few hours. In fact I could observe the slow drift of the DDS (sub 0.01Hz over several minutes) either that or the PIC clock crystal drifting, or both I guess. I tried various combinations of sample rate and shift register length but I was not able to observe a definite action at regular intervals of input frequency.  Also I noticed that the strength of the response (I mean amplitude of the heterodyne) varied a lot with the input frequency.  Some points had a very strong response for example I could sometimes get a swing of 4vp-p but at other input frequencies the heterodyne would only swing 70mV p-p near 0hz. Away from the frequency which produced a low frequency heterodyne, the integrator output tends to settle around 1/2vcc average with a small ac riding ther as the digital output is close to 50% duty cycle but obviously varies a little but you can't see it by looking at the digital XOR out directly.  I'm still scratching my head.  The output of the XOR has a very complex behavioir and I wish someone (Arv?) could help me understand it.  What I expected was that the duty cycle would vary between near zero and near 100% and be near 50% every 10hz but this clearly is not how it works. It doesn't appear that there is  strong action on the VFO other than at specific frequencies.  Once one of these critical frequencies is hit, I could see the system having a strong affect on the VFO to lock it but it doesn't look like there is much to drive it toward lock if it happens to be outside a small frequency range of a few hundredths of a hertz.  At this point I've spent enough time on this particular approach but I chose it first because it is so simple (physically at least) and I thought I could get something going with the least time and effort, which didn't turn out to be the case.  I guess I'll think about gearing up for the second H&P technique which uses a frequency counter and is more of a brute force approach.  I really wanted this shift register idea to work though as it seems elegant and deceptively simple, but obviously I have missed something critical. If anybody has a hint for me I'm all ears.

Joe ve3vxo

On Wed, Apr 10, 2019 at 10:47 AM Joe Street via Groups.Io <racingtheclouds=gmail.com@groups.io> wrote:
Hand = Hans in my last post.  Sorry Hans.

On Wed, Apr 10, 2019 at 10:45 AM Joe Street via Groups.Io <racingtheclouds=gmail.com@groups.io> wrote:
Thank you Hand for preserving a very cool bit of history so comprehensively on your website.  Chaz Fletcher G3DXZ also had a minimalist 1 chip stabilizer I thought was very clever and looks pretty easy to use although I haven't finished testing this yet.  It used a PIC processor and a software shift register and the XOR was done by using the bitwise XOR instruction as well.  The processor clock was the reference and it was divided down using a hardware timer overflow as an interrupt source which produced a sample rate of 2400hz and a lock step size of 5 hz.  Strangely the XOR instruction phase detector didn't work when the code was ported from PIC1684 to PIC16628 due to a change in the way the newer chip handles the carry bit and a work around was made using a few bit test instructions . I have ported this very simple code to PIC18 architecture as well if anybody wants it, let me know.


Joe ve3vxo

On Wed, Apr 10, 2019 at 9:55 AM Hans Summers <hans.summers@...> wrote:
Hi all

Huff & Puff was a passion of mine. I was licensed in 1994, but for various personal reasons did not go on air. I did keep reading RadCom (monthly journal of the RSGB) and was fascinated by the Huff Puff articles which appeared in Pat G3VA (SK)'s monthly "Tech Topics" column. I collected everything I could find about Huff Puff and started making my Huff Puff library, eventually putting it online on my website that I created, initially just for this purpose, in 1999. So... everything grew from these roots!

In late 2001 David WN5Y emailed me and we started discussing Huff & Puff, he was using it in his "Electroluminescent Receiver" which he still to this day sells as a kit see http://www.pan-tex.net/usr/r/receivers/index.htm - and I actually finally purchased one of his kits a year ago but still have not finished building it! Anyway - as a result of that correspondence, I decided to also build my first Huff Puff circuit. It was also the first time I had built ANYTHING at all for 8 years. I wanted to try the magnetic field method of varying inductor core permeability that David used. The result was my stabilizer http://hanssummers.com/huffpuff/fast.html and I built a 14MHz VFO that was stabilized by this circuit. 

That then became, with a mixture of other circuits also from Pat G3VA (RIP)'s column - such as the Tayloe detector (Quadrature Sampling Detector) and Polyphase networks - my first amateur radio receiver which you can read about here: http://hanssummers.com/polyphase
Then I built my 1-valve (tube) CW transmitter http://hanssummers.com/cwtx which was also from G3VA's column. 
My ATU was built around 1984 and was also a RadCom project at some point see http://hanssummers.com/atu 

That was the station, in March 2002, that I used for my first ever QSO see http://www.hanssummers.com/cwtx/cwtxfirstqso.html 

So. This Huff Puff stuff is a very important part of my personal radio history. Later, the hanssummers.com website was expanded to include lots of old projects, and I started adding new ones... so really 2002 was the birth of my amateur radio life. 

Anyway I wanted to say a few things about Huff Puff. 

1. PLL vs FLL is a debate that raged on sometimes (PLL = Phase Locked Loop, FLL = Frequency Locked Loop). A Huff Puff circuit is not exactly like either. You can make a reasonably convincing argument for why it is not a PLL or why it is not a FLL. However if the assumption, from your proof that it is not a PLL, is that therefore it must be a FLL... or vice versa - then you probably start falling into difficulty. I think not everything is as simply classifiable into one of two categories. 

2. A Huff Puff circuit doesn't exactly lock a VFO precisely on any particular frequency. What it does is compare pulse edges and try to line up the pulse edges. One is a divided down timebase, the other is the VFO. Actually which one is divided down can be swapped. It is continually hunting, around a target frequency. There are multiple stable target frequencies, separated by typically 10, 20, 30Hz etc depending on how your circuit is designed. The Huff Puff circuit will try to steer the frequency to the nearest target frequency. 

3. One critical aspect of Huff Puff is that the correction power of the circuit must be sufficient to correct any drift occurring, but not so aggressive that it overcompensates or that it does not allow you to tune the VFO normally. This is quite hard to set up properly. If the correction capability of the Huff Puff is too weak, then the VFO my drift far enough before being corrected, that the Huff Puff circuit "jumps" to trying to move it to the next stable target frequency. If the correction capability is too strong then it would make it hard for you to manually tune the VFO; additionally it makes for large excursions around the target frequency (which if extreme, could also make it "jump" to the next target frequency. 

4. If correctly set up, the Huff Puff circuit does not add much in the way of any objectionable sidebands or phase noise. In the days when PLL synthesizers were often not well designed, leading to quite high levels of phase noise, the way a Huff Puff circuit retains the cleanliness of the underlying VFO was said to be one of the advantages. That and the inherent simplicity (low parts count, at least). 

5. As Allison KB1GMX said, and what Pat G3VA said before, something like: "A Huff Puff circuit does not turn a bad VFO into a good VFO; it turns a good VFO into a better VFO". Every effort should be made, to make the VFO as good as possible before trying to add a Huff Puff circuit to make it really perfect! 

6. The "Fast" style Huff Puff circuit developed initially by Peter G7IXH, is effectively like an array of ordinary stabilizers all acting in parallel on the same VFO. What it allows you to do, is
a) stabilize a worse VFO 
b) stabilize a good VFO better
Using it for a) is not a good idea, according to the make-the-VFO-as-good-as-possible-first principle. Stabilizing a good VFO better, means that you can make the Huff Puff corrections much smaller, it means that the frequency excursions become a lot smaller. The circuit is also a lot more forgiving when setting it up. 

7. Some practical and simple designs I worked on are here: http://www.hanssummers.com/huffpuff/minimalist.html , which are targeted towards minimalist implementations. The 1-chip version http://www.hanssummers.com/huffpuff/minimalist/1chip was an experiment to really see how far a Huff Puff stabilizer can be minimized. It is very inefficient and not easy to set up. I don't recommend it for other than curiosity value. The 2-chip "Fast" type http://www.hanssummers.com/huffpuff/minimalist/2chipfast.html with discrete-component XOR gate (though an ordinary XOR gate could also be used) is a good circuit, it works reliably and efficiently and isn't fussy to set up. 

Overall Huff & Puff circuits are a bit dated now but who cares, they are really fascinating to play with and very educational. 

73 Hans G0UPL


Re: Qrp-labs and a Huff and Puff circuit board

Arv Evans <arvid.evans@...>
 

Joe

Congratulations.  Sounds like you are well on the way to becoming more stable...!
The start at zero versus start at 1 is a very common error.  Even the experts do
that frequently.  We count by ones, but computers do it with zeros and non-zeros.

Once you have all this worked out I suspect that there will be some interest by others
to use you design for tube-type rigs, and for solid state analog VFO units. 

Arv
_._


On Sat, Apr 13, 2019 at 4:23 PM Joe Street <racingtheclouds@...> wrote:
Hold the phone Arv!  On a hunch I thought what if the way the shift register is being handled is messed up somehow, and sure enough it was.  In porting the code to the new architecture I defined a length variable and added it to the start address of the array when I should have added (length -1).  Duh.  A real newby error.  So it was XOR'ing the current logic state with a fixed bit from memory.  No wonder it was mostly unresponsive except at specific frequencies (probably harmonically related to the processor clock).  Now that I have fixed that I get the expected behaviour, and every 5 hz the integrated output changes direction (increasing vs decreasing) repeating the cycle every 10Hz.  YAY!  What an elegant design.  Now to build the VFO and get on with that part.

Joe

On Sat, Apr 13, 2019 at 5:12 PM Arv Evans <arvid.evans@...> wrote:
Joe

I may not be of much help here.  I was assuming that your design was a traditional H&P
layout.  You did express yourself well, I just did not read it well. 

The G4DXZ design is PIC based with most of the heavy lifting being done inside the
micro-processor itself.  This gets involved with Nyquist speed in both hardware and software. 
Several years back Ian K3IMW did send me a PIC with the G3DXF stabilizer software installed.
It worked so well that I did not really get involved with the how or why it did so. 

Arv
_._


On Sat, Apr 13, 2019 at 2:42 PM Joe Street <racingtheclouds@...> wrote:
Hi Arv

I think I didn't express it well.  All the functionality is internal to the microprocessor except for an RC integrator on the output pin.  So a timer is setup to generate a hardware interrupt at the chosen sample rate (2929.6hz in this case).  In the interrupt service routine the logic state at the frequency input pin is sampled and it is either logic high or low at that instant. The logic state is saved and shifted into a memory based delay line or shift register in this case with 296 stages and all the bits get shifted once per sample period.  The last thing the service routine does is compare the current logic state to the last bit in the shift register after shifting and do an exclusive or. Then the processor simply loops doing nothing till the next timer interrupt.  The logical output of the XOR is a toggling bit stream sent to the output port pin and yes it is either high or low but if you filter it with a long timebase RC you get a DC value proportional to the duty cycle of that output bit.  What I am finding is that close to certain frequencies the duty cycle changes rapidly with a very small shift in input frequency. This I take it is the action which causes frequency lock as the filtered output is supposed to ultimately drive a varactor in the VFO.  If I deviate the input frequency below said frequency the duty cycle goes toward 0% which integrates to a DC value near ground and if I deviate the input frequency a little above said frequency then the duty cycle tends toward 100% which gives a DC level near Vcc which would increase capacitance in the varactor and drive the frequency back down.  However outside of this small input frequency range the duty cycle tends to be close to 50% for a broad range of input frequencies which means the integrator output sits near Vcc/2.  When I read about this technique I imagined that since the code is designed to create a 10 hz lock step I should see the duty cycle range between its high and low extent in a cyclical way every 10Hz as I vary the input frequecy, but it is not the case.  Imagine I start to increase the input frequency till the DC level gets to Vcc (tries to drive the VFO back down) but if I keep going shouldn't the duty cycle suddenly flip at some point causing the integrated DC to drive low and thus reducing the varactor capacitance and thereby driving the VFO frequency UP to the next lock point?  I know I am testing this thing open loop but if it is going to work the way it is described, shouldn't I see the behaviour I just described repeating every 10Hz as I sweep the input frequency?

Here is the paper I am working from which describes the code I downloaded.  http://www.hanssummers.com/images/stories/library/ttjun07.pdf

Joe

On Sat, Apr 13, 2019 at 2:23 PM Arv Evans <arvid.evans@...> wrote:
Joe

Output of the leading/lagging slicer should be either high or low...no in-between state.
I would start troubleshooting that area. 

If using a D-type FF for the comparison function...its outputs can only be high or low.  There
is no analog output in these circuits.  On a slow scope or voltmeter the output can appear
to be vcc/2 if it is changing rapidly enough to be averaging in the test instrument.
If the VFO input is always higher than the reference transition the D-type FF output should
always be one polarity, depending on which output you use.  If always lower then the polarity
should always be the same but opposite polarity.


Arv
_._


On Sat, Apr 13, 2019 at 12:07 PM Joe Street <racingtheclouds@...> wrote:
Thanks Arv

Yeah it is a very curious thing.  I am injecting a TTL level signal from a DDS for testing so the input level is not a factor.  What gives me doubts about continuing with this design is what is going on when there is not an obvious response action on the control output.  When the action is obvious it makes sense ie as I vary the input frequency up/dn the control output duty cycle varies from 100% to 0% and the integrated output creates a DC swing virtually rail to rail but there are also spots where the integrated output shows only a small swing around vcc/2.  Now on the scope as I vary the input up/dn I see there is definitely a point at a certain frequency where the variation in duty cycle slows and the integrated signal transitions from a sine wave to DC but the amplitude of the swing is small and therefore would have a much less powerful affect on the varactor.  Is that considered a lock point?  If you look at the digital output before the integrator you only see a square wave, the variations in the duty cycle are so small you don't notice them on the scope but you see the effect once integrated.  How this would play if I closed the loop around an actual VFO instead of testing the way I am isn't intuitively obvious.  I am tempted to put this one aside and try the one with the frequency counter which I suspect may require less black arts skills!

Joe

On Sat, Apr 13, 2019 at 1:39 PM Arv Evans <arvid.evans@...> wrote:
Joe

I have to admit that when Hans first brought H&P to my attention several years ago it took
me several months before I was forced to admit that it was not a mixer.  Key concept  is edge
alignment between the two signals (VFO and reference clock).  Once I had set aside my
own attempt to do an Arduino version and built a simple D-type FF based version, things
began to make more sense to my feeble brain. 

My first working H&P used a 32 Hz reference from a divider on a 32 KHz crystal oscillator,
with a 74HC74 as comparator and things started to work better.  From there it was just a matter
of fine tuning levels to make it actually control the VFO side of things.  Note, there is no
"lock" state in H&P.  It always slowly wanders up and down about 1 Hz around multiples
of the reference clock.  Time delay in the control loop and coupling between the varactor
and oscillator tank make its action more aggressive or less aggressive.  If too aggressive the 
frequency control will feel "sticky".  Inadequately aggressive circuits may jump tuning steps
if the VFO drift rate exceeds frequency correction rate. 

My second working version had way too much control of the VFO and refused to tune in
desired steps.  It would hold a set frequency until I had tuned the VFO several steps away
from the 32 Hz reference and then jump several steps to the nearest 32 Hz based reference
point.  After I added a series resistor in the feedback loop this build settled down and is still
being used to stabilize an old BITX40A. 

There are several ways to implement H&P.  My versions used a D-type FF to latch HIGH or LOW
based on edge comparison between the LF reference and the VFO.  Just to prove a point I did
build one that reversed the HF and LF parts by dividing the VFO down to LF and comparing that
with a HF reference clock.  That works maybe better for my friends in Australia and New Zealand
where things are normally upside down.   8-)

Other versions of H&P are set up to always push or pull the frequency in one direction, with drift
compensation adjusted to always drift in the opposite direction.  That just confused me so I
mostly avoided this idea.

It should be possible to use some sort of discrete component multi-vibrator circuit to replace
the comparison latch.  This might be a valid approach for tube-type VFOs where the voltages
are higher than nominally 5V TTL levels.  I did model this in LTSpice but never actually built one. 

H&P is sensitive to signal levels because this affects the point where the latch (D-type FF)
senses leading or lagging conditions and toggles its output accordingly.  Adding a Schmidt-trigger
CMOS gate(s) ahead of the latch  inputs could minimize this and might reduce any jitter output
from the phase comparison action.

All of the several H&P circuits that I have built required some fine-tuning before they would
work properly.  This adds credibility to Hans` statement about H&P probably not being
something that could be offered as a kit that others could just plug into existing circuits and
expect it to work first try. 

I did go back to an Arduino based FLL (not H&P) design that counts VFO frequency and
compares that with a user-entered frequency value.  This is an easier thing to get working
and it does have 3-states (too high, locked, and too low).  This does not have set tuning steps
unless you design that into the software side of things.  Tuning rate can be made variable
based on how far off-frequency the measured VFO might be.  Some may disagree but this
seems closer to an FLL than a traditional H&P design. 

There are micro-controller based stabilizers that claim to be H&P but I have never seriously
tried to use or duplicate them. 

Don't know if any of this is helpful.  H&P is an interesting concept, and one that can be
implemented successfully if time is taken to fully understand how it works and to fine-tune
the circuitry.

Arv
_._

On Sat, Apr 13, 2019 at 9:48 AM Joe Street <racingtheclouds@...> wrote:
Well last night I had a bit of a play around with the software type shift register and XOR implementation using a Sparkfun UBW board which has a PIC18 processor and a 24MHz crystal.  G3DXZ originally ran this on a PIC16 architecture with a much lower frequency crystal to get a 5Hz lock step, but I used an internal prescaler to get a very close RF sample rate of 2929.6 Hz and a shift register size of 296 bits (37 bytes) so this, according to the lore, should result in a lock step size of 2929.6 / 296 = 9.89 Hz which is as close as I could get to 10hz with this particular crystal and approach.  If I modified the code I could reduce the shift reg to 293 bits and get 9.998Hz but it is written to use a shift register which is a full multiple of 8 bits so I stuck with that and went ahead and did some testing.  Ironically today I can feed a test signal from a DDS source with high stability and adjust the frequency in 0.01Hz steps and observe the control output with the system open loop.  I used an integrator of 390Kohm feeding a 1uF on the output.  What I saw on the scope was fascinating but unfortunately I'm still a little perplexed about how this technique works!  What I observed was that the integrated output produces a heterodyne, the frequency of which is highly responsive to the exact frequency at the input and increases in amplitude as the heterodyne approaches 0 Hz.  However, I expected this behaviour to be cyclical and repeat at intervals of 9.9hz, which it did not.  It is difficult to find these lock points as they are extremely sensitive to very small changes in frequency at the input and the amplitude of the observed heterodyne diminishes rapidly as its frequency departs from DC either side and this happens within a few 0.01hz steps change of input frequency up or down from the DC output point!  So scanning the input frequency in 1 hz steps, you easily miss a strong response on the control output. At first I didn't think it was working at all and that there was a mistake in porting the code to the new architecture, but then I realized I needed to vary the input frequency much more slowly than I was.  This was fascinating and I played around for a few hours. In fact I could observe the slow drift of the DDS (sub 0.01Hz over several minutes) either that or the PIC clock crystal drifting, or both I guess. I tried various combinations of sample rate and shift register length but I was not able to observe a definite action at regular intervals of input frequency.  Also I noticed that the strength of the response (I mean amplitude of the heterodyne) varied a lot with the input frequency.  Some points had a very strong response for example I could sometimes get a swing of 4vp-p but at other input frequencies the heterodyne would only swing 70mV p-p near 0hz. Away from the frequency which produced a low frequency heterodyne, the integrator output tends to settle around 1/2vcc average with a small ac riding ther as the digital output is close to 50% duty cycle but obviously varies a little but you can't see it by looking at the digital XOR out directly.  I'm still scratching my head.  The output of the XOR has a very complex behavioir and I wish someone (Arv?) could help me understand it.  What I expected was that the duty cycle would vary between near zero and near 100% and be near 50% every 10hz but this clearly is not how it works. It doesn't appear that there is  strong action on the VFO other than at specific frequencies.  Once one of these critical frequencies is hit, I could see the system having a strong affect on the VFO to lock it but it doesn't look like there is much to drive it toward lock if it happens to be outside a small frequency range of a few hundredths of a hertz.  At this point I've spent enough time on this particular approach but I chose it first because it is so simple (physically at least) and I thought I could get something going with the least time and effort, which didn't turn out to be the case.  I guess I'll think about gearing up for the second H&P technique which uses a frequency counter and is more of a brute force approach.  I really wanted this shift register idea to work though as it seems elegant and deceptively simple, but obviously I have missed something critical. If anybody has a hint for me I'm all ears.

Joe ve3vxo

On Wed, Apr 10, 2019 at 10:47 AM Joe Street via Groups.Io <racingtheclouds=gmail.com@groups.io> wrote:
Hand = Hans in my last post.  Sorry Hans.

On Wed, Apr 10, 2019 at 10:45 AM Joe Street via Groups.Io <racingtheclouds=gmail.com@groups.io> wrote:
Thank you Hand for preserving a very cool bit of history so comprehensively on your website.  Chaz Fletcher G3DXZ also had a minimalist 1 chip stabilizer I thought was very clever and looks pretty easy to use although I haven't finished testing this yet.  It used a PIC processor and a software shift register and the XOR was done by using the bitwise XOR instruction as well.  The processor clock was the reference and it was divided down using a hardware timer overflow as an interrupt source which produced a sample rate of 2400hz and a lock step size of 5 hz.  Strangely the XOR instruction phase detector didn't work when the code was ported from PIC1684 to PIC16628 due to a change in the way the newer chip handles the carry bit and a work around was made using a few bit test instructions . I have ported this very simple code to PIC18 architecture as well if anybody wants it, let me know.


Joe ve3vxo

On Wed, Apr 10, 2019 at 9:55 AM Hans Summers <hans.summers@...> wrote:
Hi all

Huff & Puff was a passion of mine. I was licensed in 1994, but for various personal reasons did not go on air. I did keep reading RadCom (monthly journal of the RSGB) and was fascinated by the Huff Puff articles which appeared in Pat G3VA (SK)'s monthly "Tech Topics" column. I collected everything I could find about Huff Puff and started making my Huff Puff library, eventually putting it online on my website that I created, initially just for this purpose, in 1999. So... everything grew from these roots!

In late 2001 David WN5Y emailed me and we started discussing Huff & Puff, he was using it in his "Electroluminescent Receiver" which he still to this day sells as a kit see http://www.pan-tex.net/usr/r/receivers/index.htm - and I actually finally purchased one of his kits a year ago but still have not finished building it! Anyway - as a result of that correspondence, I decided to also build my first Huff Puff circuit. It was also the first time I had built ANYTHING at all for 8 years. I wanted to try the magnetic field method of varying inductor core permeability that David used. The result was my stabilizer http://hanssummers.com/huffpuff/fast.html and I built a 14MHz VFO that was stabilized by this circuit. 

That then became, with a mixture of other circuits also from Pat G3VA (RIP)'s column - such as the Tayloe detector (Quadrature Sampling Detector) and Polyphase networks - my first amateur radio receiver which you can read about here: http://hanssummers.com/polyphase
Then I built my 1-valve (tube) CW transmitter http://hanssummers.com/cwtx which was also from G3VA's column. 
My ATU was built around 1984 and was also a RadCom project at some point see http://hanssummers.com/atu 

That was the station, in March 2002, that I used for my first ever QSO see http://www.hanssummers.com/cwtx/cwtxfirstqso.html 

So. This Huff Puff stuff is a very important part of my personal radio history. Later, the hanssummers.com website was expanded to include lots of old projects, and I started adding new ones... so really 2002 was the birth of my amateur radio life. 

Anyway I wanted to say a few things about Huff Puff. 

1. PLL vs FLL is a debate that raged on sometimes (PLL = Phase Locked Loop, FLL = Frequency Locked Loop). A Huff Puff circuit is not exactly like either. You can make a reasonably convincing argument for why it is not a PLL or why it is not a FLL. However if the assumption, from your proof that it is not a PLL, is that therefore it must be a FLL... or vice versa - then you probably start falling into difficulty. I think not everything is as simply classifiable into one of two categories. 

2. A Huff Puff circuit doesn't exactly lock a VFO precisely on any particular frequency. What it does is compare pulse edges and try to line up the pulse edges. One is a divided down timebase, the other is the VFO. Actually which one is divided down can be swapped. It is continually hunting, around a target frequency. There are multiple stable target frequencies, separated by typically 10, 20, 30Hz etc depending on how your circuit is designed. The Huff Puff circuit will try to steer the frequency to the nearest target frequency. 

3. One critical aspect of Huff Puff is that the correction power of the circuit must be sufficient to correct any drift occurring, but not so aggressive that it overcompensates or that it does not allow you to tune the VFO normally. This is quite hard to set up properly. If the correction capability of the Huff Puff is too weak, then the VFO my drift far enough before being corrected, that the Huff Puff circuit "jumps" to trying to move it to the next stable target frequency. If the correction capability is too strong then it would make it hard for you to manually tune the VFO; additionally it makes for large excursions around the target frequency (which if extreme, could also make it "jump" to the next target frequency. 

4. If correctly set up, the Huff Puff circuit does not add much in the way of any objectionable sidebands or phase noise. In the days when PLL synthesizers were often not well designed, leading to quite high levels of phase noise, the way a Huff Puff circuit retains the cleanliness of the underlying VFO was said to be one of the advantages. That and the inherent simplicity (low parts count, at least). 

5. As Allison KB1GMX said, and what Pat G3VA said before, something like: "A Huff Puff circuit does not turn a bad VFO into a good VFO; it turns a good VFO into a better VFO". Every effort should be made, to make the VFO as good as possible before trying to add a Huff Puff circuit to make it really perfect! 

6. The "Fast" style Huff Puff circuit developed initially by Peter G7IXH, is effectively like an array of ordinary stabilizers all acting in parallel on the same VFO. What it allows you to do, is
a) stabilize a worse VFO 
b) stabilize a good VFO better
Using it for a) is not a good idea, according to the make-the-VFO-as-good-as-possible-first principle. Stabilizing a good VFO better, means that you can make the Huff Puff corrections much smaller, it means that the frequency excursions become a lot smaller. The circuit is also a lot more forgiving when setting it up. 

7. Some practical and simple designs I worked on are here: http://www.hanssummers.com/huffpuff/minimalist.html , which are targeted towards minimalist implementations. The 1-chip version http://www.hanssummers.com/huffpuff/minimalist/1chip was an experiment to really see how far a Huff Puff stabilizer can be minimized. It is very inefficient and not easy to set up. I don't recommend it for other than curiosity value. The 2-chip "Fast" type http://www.hanssummers.com/huffpuff/minimalist/2chipfast.html with discrete-component XOR gate (though an ordinary XOR gate could also be used) is a good circuit, it works reliably and efficiently and isn't fussy to set up. 

Overall Huff & Puff circuits are a bit dated now but who cares, they are really fascinating to play with and very educational. 

73 Hans G0UPL


Re: Qrp-labs and a Huff and Puff circuit board

Joe Street
 

Hold the phone Arv!  On a hunch I thought what if the way the shift register is being handled is messed up somehow, and sure enough it was.  In porting the code to the new architecture I defined a length variable and added it to the start address of the array when I should have added (length -1).  Duh.  A real newby error.  So it was XOR'ing the current logic state with a fixed bit from memory.  No wonder it was mostly unresponsive except at specific frequencies (probably harmonically related to the processor clock).  Now that I have fixed that I get the expected behaviour, and every 5 hz the integrated output changes direction (increasing vs decreasing) repeating the cycle every 10Hz.  YAY!  What an elegant design.  Now to build the VFO and get on with that part.

Joe


On Sat, Apr 13, 2019 at 5:12 PM Arv Evans <arvid.evans@...> wrote:
Joe

I may not be of much help here.  I was assuming that your design was a traditional H&P
layout.  You did express yourself well, I just did not read it well. 

The G4DXZ design is PIC based with most of the heavy lifting being done inside the
micro-processor itself.  This gets involved with Nyquist speed in both hardware and software. 
Several years back Ian K3IMW did send me a PIC with the G3DXF stabilizer software installed.
It worked so well that I did not really get involved with the how or why it did so. 

Arv
_._


On Sat, Apr 13, 2019 at 2:42 PM Joe Street <racingtheclouds@...> wrote:
Hi Arv

I think I didn't express it well.  All the functionality is internal to the microprocessor except for an RC integrator on the output pin.  So a timer is setup to generate a hardware interrupt at the chosen sample rate (2929.6hz in this case).  In the interrupt service routine the logic state at the frequency input pin is sampled and it is either logic high or low at that instant. The logic state is saved and shifted into a memory based delay line or shift register in this case with 296 stages and all the bits get shifted once per sample period.  The last thing the service routine does is compare the current logic state to the last bit in the shift register after shifting and do an exclusive or. Then the processor simply loops doing nothing till the next timer interrupt.  The logical output of the XOR is a toggling bit stream sent to the output port pin and yes it is either high or low but if you filter it with a long timebase RC you get a DC value proportional to the duty cycle of that output bit.  What I am finding is that close to certain frequencies the duty cycle changes rapidly with a very small shift in input frequency. This I take it is the action which causes frequency lock as the filtered output is supposed to ultimately drive a varactor in the VFO.  If I deviate the input frequency below said frequency the duty cycle goes toward 0% which integrates to a DC value near ground and if I deviate the input frequency a little above said frequency then the duty cycle tends toward 100% which gives a DC level near Vcc which would increase capacitance in the varactor and drive the frequency back down.  However outside of this small input frequency range the duty cycle tends to be close to 50% for a broad range of input frequencies which means the integrator output sits near Vcc/2.  When I read about this technique I imagined that since the code is designed to create a 10 hz lock step I should see the duty cycle range between its high and low extent in a cyclical way every 10Hz as I vary the input frequecy, but it is not the case.  Imagine I start to increase the input frequency till the DC level gets to Vcc (tries to drive the VFO back down) but if I keep going shouldn't the duty cycle suddenly flip at some point causing the integrated DC to drive low and thus reducing the varactor capacitance and thereby driving the VFO frequency UP to the next lock point?  I know I am testing this thing open loop but if it is going to work the way it is described, shouldn't I see the behaviour I just described repeating every 10Hz as I sweep the input frequency?

Here is the paper I am working from which describes the code I downloaded.  http://www.hanssummers.com/images/stories/library/ttjun07.pdf

Joe

On Sat, Apr 13, 2019 at 2:23 PM Arv Evans <arvid.evans@...> wrote:
Joe

Output of the leading/lagging slicer should be either high or low...no in-between state.
I would start troubleshooting that area. 

If using a D-type FF for the comparison function...its outputs can only be high or low.  There
is no analog output in these circuits.  On a slow scope or voltmeter the output can appear
to be vcc/2 if it is changing rapidly enough to be averaging in the test instrument.
If the VFO input is always higher than the reference transition the D-type FF output should
always be one polarity, depending on which output you use.  If always lower then the polarity
should always be the same but opposite polarity.


Arv
_._


On Sat, Apr 13, 2019 at 12:07 PM Joe Street <racingtheclouds@...> wrote:
Thanks Arv

Yeah it is a very curious thing.  I am injecting a TTL level signal from a DDS for testing so the input level is not a factor.  What gives me doubts about continuing with this design is what is going on when there is not an obvious response action on the control output.  When the action is obvious it makes sense ie as I vary the input frequency up/dn the control output duty cycle varies from 100% to 0% and the integrated output creates a DC swing virtually rail to rail but there are also spots where the integrated output shows only a small swing around vcc/2.  Now on the scope as I vary the input up/dn I see there is definitely a point at a certain frequency where the variation in duty cycle slows and the integrated signal transitions from a sine wave to DC but the amplitude of the swing is small and therefore would have a much less powerful affect on the varactor.  Is that considered a lock point?  If you look at the digital output before the integrator you only see a square wave, the variations in the duty cycle are so small you don't notice them on the scope but you see the effect once integrated.  How this would play if I closed the loop around an actual VFO instead of testing the way I am isn't intuitively obvious.  I am tempted to put this one aside and try the one with the frequency counter which I suspect may require less black arts skills!

Joe

On Sat, Apr 13, 2019 at 1:39 PM Arv Evans <arvid.evans@...> wrote:
Joe

I have to admit that when Hans first brought H&P to my attention several years ago it took
me several months before I was forced to admit that it was not a mixer.  Key concept  is edge
alignment between the two signals (VFO and reference clock).  Once I had set aside my
own attempt to do an Arduino version and built a simple D-type FF based version, things
began to make more sense to my feeble brain. 

My first working H&P used a 32 Hz reference from a divider on a 32 KHz crystal oscillator,
with a 74HC74 as comparator and things started to work better.  From there it was just a matter
of fine tuning levels to make it actually control the VFO side of things.  Note, there is no
"lock" state in H&P.  It always slowly wanders up and down about 1 Hz around multiples
of the reference clock.  Time delay in the control loop and coupling between the varactor
and oscillator tank make its action more aggressive or less aggressive.  If too aggressive the 
frequency control will feel "sticky".  Inadequately aggressive circuits may jump tuning steps
if the VFO drift rate exceeds frequency correction rate. 

My second working version had way too much control of the VFO and refused to tune in
desired steps.  It would hold a set frequency until I had tuned the VFO several steps away
from the 32 Hz reference and then jump several steps to the nearest 32 Hz based reference
point.  After I added a series resistor in the feedback loop this build settled down and is still
being used to stabilize an old BITX40A. 

There are several ways to implement H&P.  My versions used a D-type FF to latch HIGH or LOW
based on edge comparison between the LF reference and the VFO.  Just to prove a point I did
build one that reversed the HF and LF parts by dividing the VFO down to LF and comparing that
with a HF reference clock.  That works maybe better for my friends in Australia and New Zealand
where things are normally upside down.   8-)

Other versions of H&P are set up to always push or pull the frequency in one direction, with drift
compensation adjusted to always drift in the opposite direction.  That just confused me so I
mostly avoided this idea.

It should be possible to use some sort of discrete component multi-vibrator circuit to replace
the comparison latch.  This might be a valid approach for tube-type VFOs where the voltages
are higher than nominally 5V TTL levels.  I did model this in LTSpice but never actually built one. 

H&P is sensitive to signal levels because this affects the point where the latch (D-type FF)
senses leading or lagging conditions and toggles its output accordingly.  Adding a Schmidt-trigger
CMOS gate(s) ahead of the latch  inputs could minimize this and might reduce any jitter output
from the phase comparison action.

All of the several H&P circuits that I have built required some fine-tuning before they would
work properly.  This adds credibility to Hans` statement about H&P probably not being
something that could be offered as a kit that others could just plug into existing circuits and
expect it to work first try. 

I did go back to an Arduino based FLL (not H&P) design that counts VFO frequency and
compares that with a user-entered frequency value.  This is an easier thing to get working
and it does have 3-states (too high, locked, and too low).  This does not have set tuning steps
unless you design that into the software side of things.  Tuning rate can be made variable
based on how far off-frequency the measured VFO might be.  Some may disagree but this
seems closer to an FLL than a traditional H&P design. 

There are micro-controller based stabilizers that claim to be H&P but I have never seriously
tried to use or duplicate them. 

Don't know if any of this is helpful.  H&P is an interesting concept, and one that can be
implemented successfully if time is taken to fully understand how it works and to fine-tune
the circuitry.

Arv
_._

On Sat, Apr 13, 2019 at 9:48 AM Joe Street <racingtheclouds@...> wrote:
Well last night I had a bit of a play around with the software type shift register and XOR implementation using a Sparkfun UBW board which has a PIC18 processor and a 24MHz crystal.  G3DXZ originally ran this on a PIC16 architecture with a much lower frequency crystal to get a 5Hz lock step, but I used an internal prescaler to get a very close RF sample rate of 2929.6 Hz and a shift register size of 296 bits (37 bytes) so this, according to the lore, should result in a lock step size of 2929.6 / 296 = 9.89 Hz which is as close as I could get to 10hz with this particular crystal and approach.  If I modified the code I could reduce the shift reg to 293 bits and get 9.998Hz but it is written to use a shift register which is a full multiple of 8 bits so I stuck with that and went ahead and did some testing.  Ironically today I can feed a test signal from a DDS source with high stability and adjust the frequency in 0.01Hz steps and observe the control output with the system open loop.  I used an integrator of 390Kohm feeding a 1uF on the output.  What I saw on the scope was fascinating but unfortunately I'm still a little perplexed about how this technique works!  What I observed was that the integrated output produces a heterodyne, the frequency of which is highly responsive to the exact frequency at the input and increases in amplitude as the heterodyne approaches 0 Hz.  However, I expected this behaviour to be cyclical and repeat at intervals of 9.9hz, which it did not.  It is difficult to find these lock points as they are extremely sensitive to very small changes in frequency at the input and the amplitude of the observed heterodyne diminishes rapidly as its frequency departs from DC either side and this happens within a few 0.01hz steps change of input frequency up or down from the DC output point!  So scanning the input frequency in 1 hz steps, you easily miss a strong response on the control output. At first I didn't think it was working at all and that there was a mistake in porting the code to the new architecture, but then I realized I needed to vary the input frequency much more slowly than I was.  This was fascinating and I played around for a few hours. In fact I could observe the slow drift of the DDS (sub 0.01Hz over several minutes) either that or the PIC clock crystal drifting, or both I guess. I tried various combinations of sample rate and shift register length but I was not able to observe a definite action at regular intervals of input frequency.  Also I noticed that the strength of the response (I mean amplitude of the heterodyne) varied a lot with the input frequency.  Some points had a very strong response for example I could sometimes get a swing of 4vp-p but at other input frequencies the heterodyne would only swing 70mV p-p near 0hz. Away from the frequency which produced a low frequency heterodyne, the integrator output tends to settle around 1/2vcc average with a small ac riding ther as the digital output is close to 50% duty cycle but obviously varies a little but you can't see it by looking at the digital XOR out directly.  I'm still scratching my head.  The output of the XOR has a very complex behavioir and I wish someone (Arv?) could help me understand it.  What I expected was that the duty cycle would vary between near zero and near 100% and be near 50% every 10hz but this clearly is not how it works. It doesn't appear that there is  strong action on the VFO other than at specific frequencies.  Once one of these critical frequencies is hit, I could see the system having a strong affect on the VFO to lock it but it doesn't look like there is much to drive it toward lock if it happens to be outside a small frequency range of a few hundredths of a hertz.  At this point I've spent enough time on this particular approach but I chose it first because it is so simple (physically at least) and I thought I could get something going with the least time and effort, which didn't turn out to be the case.  I guess I'll think about gearing up for the second H&P technique which uses a frequency counter and is more of a brute force approach.  I really wanted this shift register idea to work though as it seems elegant and deceptively simple, but obviously I have missed something critical. If anybody has a hint for me I'm all ears.

Joe ve3vxo

On Wed, Apr 10, 2019 at 10:47 AM Joe Street via Groups.Io <racingtheclouds=gmail.com@groups.io> wrote:
Hand = Hans in my last post.  Sorry Hans.

On Wed, Apr 10, 2019 at 10:45 AM Joe Street via Groups.Io <racingtheclouds=gmail.com@groups.io> wrote:
Thank you Hand for preserving a very cool bit of history so comprehensively on your website.  Chaz Fletcher G3DXZ also had a minimalist 1 chip stabilizer I thought was very clever and looks pretty easy to use although I haven't finished testing this yet.  It used a PIC processor and a software shift register and the XOR was done by using the bitwise XOR instruction as well.  The processor clock was the reference and it was divided down using a hardware timer overflow as an interrupt source which produced a sample rate of 2400hz and a lock step size of 5 hz.  Strangely the XOR instruction phase detector didn't work when the code was ported from PIC1684 to PIC16628 due to a change in the way the newer chip handles the carry bit and a work around was made using a few bit test instructions . I have ported this very simple code to PIC18 architecture as well if anybody wants it, let me know.


Joe ve3vxo

On Wed, Apr 10, 2019 at 9:55 AM Hans Summers <hans.summers@...> wrote:
Hi all

Huff & Puff was a passion of mine. I was licensed in 1994, but for various personal reasons did not go on air. I did keep reading RadCom (monthly journal of the RSGB) and was fascinated by the Huff Puff articles which appeared in Pat G3VA (SK)'s monthly "Tech Topics" column. I collected everything I could find about Huff Puff and started making my Huff Puff library, eventually putting it online on my website that I created, initially just for this purpose, in 1999. So... everything grew from these roots!

In late 2001 David WN5Y emailed me and we started discussing Huff & Puff, he was using it in his "Electroluminescent Receiver" which he still to this day sells as a kit see http://www.pan-tex.net/usr/r/receivers/index.htm - and I actually finally purchased one of his kits a year ago but still have not finished building it! Anyway - as a result of that correspondence, I decided to also build my first Huff Puff circuit. It was also the first time I had built ANYTHING at all for 8 years. I wanted to try the magnetic field method of varying inductor core permeability that David used. The result was my stabilizer http://hanssummers.com/huffpuff/fast.html and I built a 14MHz VFO that was stabilized by this circuit. 

That then became, with a mixture of other circuits also from Pat G3VA (RIP)'s column - such as the Tayloe detector (Quadrature Sampling Detector) and Polyphase networks - my first amateur radio receiver which you can read about here: http://hanssummers.com/polyphase
Then I built my 1-valve (tube) CW transmitter http://hanssummers.com/cwtx which was also from G3VA's column. 
My ATU was built around 1984 and was also a RadCom project at some point see http://hanssummers.com/atu 

That was the station, in March 2002, that I used for my first ever QSO see http://www.hanssummers.com/cwtx/cwtxfirstqso.html 

So. This Huff Puff stuff is a very important part of my personal radio history. Later, the hanssummers.com website was expanded to include lots of old projects, and I started adding new ones... so really 2002 was the birth of my amateur radio life. 

Anyway I wanted to say a few things about Huff Puff. 

1. PLL vs FLL is a debate that raged on sometimes (PLL = Phase Locked Loop, FLL = Frequency Locked Loop). A Huff Puff circuit is not exactly like either. You can make a reasonably convincing argument for why it is not a PLL or why it is not a FLL. However if the assumption, from your proof that it is not a PLL, is that therefore it must be a FLL... or vice versa - then you probably start falling into difficulty. I think not everything is as simply classifiable into one of two categories. 

2. A Huff Puff circuit doesn't exactly lock a VFO precisely on any particular frequency. What it does is compare pulse edges and try to line up the pulse edges. One is a divided down timebase, the other is the VFO. Actually which one is divided down can be swapped. It is continually hunting, around a target frequency. There are multiple stable target frequencies, separated by typically 10, 20, 30Hz etc depending on how your circuit is designed. The Huff Puff circuit will try to steer the frequency to the nearest target frequency. 

3. One critical aspect of Huff Puff is that the correction power of the circuit must be sufficient to correct any drift occurring, but not so aggressive that it overcompensates or that it does not allow you to tune the VFO normally. This is quite hard to set up properly. If the correction capability of the Huff Puff is too weak, then the VFO my drift far enough before being corrected, that the Huff Puff circuit "jumps" to trying to move it to the next stable target frequency. If the correction capability is too strong then it would make it hard for you to manually tune the VFO; additionally it makes for large excursions around the target frequency (which if extreme, could also make it "jump" to the next target frequency. 

4. If correctly set up, the Huff Puff circuit does not add much in the way of any objectionable sidebands or phase noise. In the days when PLL synthesizers were often not well designed, leading to quite high levels of phase noise, the way a Huff Puff circuit retains the cleanliness of the underlying VFO was said to be one of the advantages. That and the inherent simplicity (low parts count, at least). 

5. As Allison KB1GMX said, and what Pat G3VA said before, something like: "A Huff Puff circuit does not turn a bad VFO into a good VFO; it turns a good VFO into a better VFO". Every effort should be made, to make the VFO as good as possible before trying to add a Huff Puff circuit to make it really perfect! 

6. The "Fast" style Huff Puff circuit developed initially by Peter G7IXH, is effectively like an array of ordinary stabilizers all acting in parallel on the same VFO. What it allows you to do, is
a) stabilize a worse VFO 
b) stabilize a good VFO better
Using it for a) is not a good idea, according to the make-the-VFO-as-good-as-possible-first principle. Stabilizing a good VFO better, means that you can make the Huff Puff corrections much smaller, it means that the frequency excursions become a lot smaller. The circuit is also a lot more forgiving when setting it up. 

7. Some practical and simple designs I worked on are here: http://www.hanssummers.com/huffpuff/minimalist.html , which are targeted towards minimalist implementations. The 1-chip version http://www.hanssummers.com/huffpuff/minimalist/1chip was an experiment to really see how far a Huff Puff stabilizer can be minimized. It is very inefficient and not easy to set up. I don't recommend it for other than curiosity value. The 2-chip "Fast" type http://www.hanssummers.com/huffpuff/minimalist/2chipfast.html with discrete-component XOR gate (though an ordinary XOR gate could also be used) is a good circuit, it works reliably and efficiently and isn't fussy to set up. 

Overall Huff & Puff circuits are a bit dated now but who cares, they are really fascinating to play with and very educational. 

73 Hans G0UPL


Re: SDR Reveivers?

Shirley Dulcey KE1L
 

EMRFD is out of date in the sense that many of the designs can no
longer be built straight out of the book unless you're willing to
scrounge for NOS components. But it's EXPERIMENTAL design, so
substituting newer parts is very much in the spirit of the book.

On Sat, Apr 13, 2019 at 5:26 PM geoff M0ORE via Groups.Io
<m0ore=tiscali.co.uk@groups.io> wrote:

EMRFD is an excellent publication but the edition I use ( First Edition, 2nd printing ) has so many errors I have to check the corrections book before I trust anything just to see if an amendment has been made. The colour of the appendix CD is difficult to distinguish, why not have two colours that are opposite each other in the spectrum?

Buy it, read it, read it again.

On 13/04/2019 19:55, ajparent1/KB1GMX wrote:

John VA7JBE,

For all pass circuits look at EMRFD there is a couple of chapters and you can use the designs described.

EMRFD Experimental Methods for RF Design. Do not let the claim of old or outdated dissuade you
as knowledge does not decay.

Alllison