Re: Si5351: P1, P2, P3, what's it really all about?


Guido PE1NNZ
 

Sorry Phil,

I misread your question, so my answer does not make sense, and please reject my previous email.
It is a good question what happens for value in between 128 for P2, no idea...never tried.

On Wed, Jun 10, 2020 at 11:30 AM Guido PE1NNZ via groups.io <threeme3=gmail.com@groups.io> wrote:
Hi Phil,
This is mathematically valid, does it work? Is there anything in the datasheet or application notes which says we can't do this? Is there any effect on the jitter or other performance?
My understanding is that this allowed and works. as it meets the criteria that "a+b/c has a valid range of 15 + 0/1,048,575 and 90"  [AN619 p.3 par. 3.2].
A zero in b means that there is no fractional part involved, and improves the jitter performance, when you set FBA_INT/FBB_INT [AN619 p.4 par. 3.2.1].

BUT!! then do not start using fractional divisions on the Multi-synth dividers as the jitter is worse compared to fractional dividers in the PLL Multisynth.

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