Re: Si5351 current consumption #chat


Hans Summers
 

Hi Eduard

Another idea to check. 

There are two ways to set up the Si5351A. 

1) use a fractional feedback divider on the PLL. Then even integer for the MultiSynth. This is the method recommended by the Si documentation (and common sense intuition) for lowest jitter i.e. best phase noise performance. Furthermore this method has other advantages such as allowing the quadrature output mode used in QCX. All QRP Labs products use this way. 

2) use a fixed integer feedback on the PLL and a fractional MultiSynth divider. This is the method used by the Si5351A Linux driver that the Etherkits library was originally ported from. I'm not sure if this has been changed since then. Last time I looked at the Etherkits library it did this method 2. But I haven't looked at it for a few years and I'm sure it was improved over time. 

If one sketch is using method 1 (which I believe is by far the superior way) and the other is using method 2, it may be that this could be a factor on current consumption. I think Si do some tricks to reduce the phase noise impact of a fractional MultiSynth divider and perhaps these tricks consume some mA. There is even an "even integer MS divider" bit on the clock configuration registers. That could switch out the MS fractional MultiSynth divider cleanup stuff. 

73 Hans G0UPL 


On Sat, Mar 14, 2020, 18:27 Eduard Voiculescu <yo9ict@...> wrote:
Mike,

Do not mind about the board.

Additional functions/devices are into sleep mode or disabled completely. If you can do this measurement, stick with relative measurements between the 2 firmwares.

Shirley,

You are right.

Manually downgrading the Etherkit implementation's PLL frequency to the minimum allowed (600MHz) saves another 2mA. This is done with a simple command :
si5351.set_freq_manual(1409717000ULL, 60000000000ULL, SI5351_CLK0);

But after doing the math, the OE1CGS sketch reveals that it sets the PLL frequency much higher, at ~874MHz, while consuming less power.

I'm puzzled.

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