The biggest issue is phase jitter is essentially noise in the frequency
domain ie: FM. All of the papers that address this try to translate that
from to amplitude where noise is measured (usually). Its very system
Since the SI5351 is really a UHF PLL followed by integer or fractional
(user decides) counters its easy and hard to evaluate noise and side
bands. Every divide lowers the phase noise of the UHF VCO and the
multiply from 27mhz to PLL VCO frequency multiplys the the phase noise.
So on a 1:1 basis at 27mhz or below its likely to be as good or only slightly
poorer than the 27mhz reference. At higher than 90-100mhz you in the
path problem if even pushing the internal PLL higher to 1ghz you max
divisor is only 10 for 100mhz!
Using a SA to evaluate spurs be very careful to not introduce spurs
or worse from incorrect technique.
For those that need better there is he SI570 (also a pain to program).
Or go to a crystal and multipliers.
For those that want cheap and easy above 100mhz, sorry you need to
look at other parts if it isn't good enough for you. They exist but not
cheap and likely harder to use.
As is complaining about a device that was designed as a clock source
data systems is fortuitous for us RF weenies that it works.
Please reply on list so we can share.
No direct email, it goes to bit bucket due address harvesting in groups.IO