Re: si5351a issue spectral output above 90Mhz
toggle quoted messageShow quoted text
Hi Phil, F1US
The Si5351 contains two stages of synthesis. Note that it is incorrect to call an Si5351A a DDS (Direct Digital Synthesizer) which is a completely different synthesis technique.
The first stage is a PLL
which multiplies the 27MHz reference frequency up. There is a VCO whose output should be in the range 600-900Hz and the loop is closed by a divider which is fractional (20-bit fractional part).
The second stage is a divider block ("MultiSynth divider") which divides the VCO frequency produced in the first stage, down to the output frequency. This divider is also fractional with a 20,bit fractional part.
[For the sake of completeness I should also mention the third stage, which is a divider configurable as one of 7 powers of two from 1 to 128 - this is normally only used to achieve low frequency output, under about 1MHz].
Whilst both the first and second stage dividers have integer and fractional parts, they can both be operated with an integer division ratio, simply by setting the fractional part to zero. If both are integers, then it will not be possible to achieve fine resolution tuning, only widely spaced freqiencies will be available. So generally one or other of the two stages must be used with fractional configuration.
The datasheet recommendation for best low jitter (phase noise) performance is to use even integer division in the second stage (MutliSynth divider) which is what all the QRP Labs firmware does. There are some Si5351A libraries which do not do this, they fix the PLL divider at an integer value and use fractional division in the MultiSynth stage - these libraries will generally produce an inferior output in terms of phase noise and spurious products.
As may be expected in a PLL system, spectral purity of the Si5351A outout is better at lower frequencies than high ones.
Phil you mentioned you used the Si5351A for 212MHz output. Note that this is beyond the specified maximum 200MHz of the device. Whilst they have been found to work and be stable up to 290 or 300MHz, it is not clear what negative impact this has on performance specifications.
To give the Si5351A chip the best chance to be as clean as possible at VHF the following recommendations should be followed. Some of these apply even if you are using a complete product like ProgRock or VFO/SigGen.
1. Use a clean power supply. A noisy supply will inflict its junk on the output to some extent.
2. Use even integer division in the MultiSynth stage - if you are writing your own code and use someone else's library, try to find a decent one that doesn't do it the other way round.
3. Use load impedances of at least 1KOhms. Don't drive things like diode mixers directly, use buffers. This improves phase noise performance and eliminates cross talk problems between Si5351A outputs.
4. Use reference frequency crystals in the range 25-27MHz as specified in the Si5351A datasheet - frequencies outside this range have been found to degrade spectral purity considerably.
73 Hans G0UPL
On Mon, Jan 27, 2020, 20:52 Phil Crockford <pcc@...> wrote: