Topics

Output Impedance?

Asadullah Mir
 

Looking at the schematic of PHSNA II it seems that the output impedance is close to 73 ohms rather than 50 Ohms.

Am I right and why so?


73


Azzy

Nick Kennedy
 

I get a little confused as to which designation refers to which schematic.  Does the version you are looking at have a transistor amplifier or a MMIC?  Or does it use a DDS-60?  

Following the amplifier, what does the attenuator look like?

I think they were all designed to be close to 50 ohms.

73,

Nick, WA5BDU

On Fri, Aug 26, 2016 at 11:26 PM, mirasad314@... [PHSNA] <PHSNA@...> wrote:
 

Looking at the schematic of PHSNA II it seems that the output impedance is close to 73 ohms rather than 50 Ohms.

Am I right and why so?


73


Azzy


Asadullah Mir
 

Hi Nick
I was looking at the drawing  by Jim Gianco N51B  and Jerry Haigwood W51H
The output  attenuator is two 150 Ohm and one 39 Ohm R.
The source is ERA-3+  which has a bias resistor of 270 Ohm.
Essentially since the output impedance of the MMIC is rather high the shunt of 270 Ohm prevails so this attenuater has one side fed from source impedance of 270 ohms and looking in from the output side the impedance calculates to 71 Ohm.
this is (270 || 150) +39) || (150) Ohm.

Return loss on output of ERA3 is >quoted at 21db at 1 GHz so if I assume output impedance of 
50 ohms
then (  (270 || 50 ||150) +39  || 150)  = 63 ohms.


I think there is another  output  type too and I think a quick mental calculation showed that one to be 73 Ohm but I will check a post a little later.

 I might be wrong
73

Azzy

( Was AP2AM.  Haven't got new CS yet))

Asadullah Mir
 

Hi Nick sorry about that I checked my calc with S22=>21db
The impedance calculates to >48 Ohm. Which is great.
Sorry about that.
(  (270 || 50 ||150) +39  || 150)  = 48.61 ohms.  is the correct way.

Thanks
73


Nick Kennedy
 

Well, I was following along with your reasoning and it made sense to me. From the diagram of the internals of the MMIC in the data sheet, it appeared the output is taken from the collector(s), so it made sense that the resistance would be determined by the external collector resistor.  But having a high return loss looking in does imply an inherent 50 ohm source resistance. Somehow(?)

The schematic I'm looking at is different.  I need some more versions. This one is Rev 6.06 of May 4, 2014. It does have an ERA-3+, but it has an RFC in series with the 270 ohm biasing resistor, essentially eliminating its effect on Rg. 

And the pi attenuator in this revision has resistances of 82, 93.1, 82 ohms, which will give 50 ohms looking in if there's a source resistance of 50 on the other end.

Oh - I see that it specifies values of 150, 39, 150 as a -6 dB option for the -12 dB attenuator shown.

73-

Nick, WA5BDU

On Sat, Aug 27, 2016 at 12:47 PM, mirasad314@... [PHSNA] <PHSNA@...> wrote:
 

Hi Nick sorry about that I checked my calc with S22=>21db

The impedance calculates to >48 Ohm. Which is great.
Sorry about that.
(  (270 || 50 ||150) +39  || 150)  = 48.61 ohms.  is the correct way.

Thanks
73



Asadullah Mir
 

Hi Nick!

 I too was wondering how theS22 is +- 50Ohms.

On the other hand I am wondering why was an MMIC used in the first place. I can get equally good results if I directly use the 9851 output. A match with a 4:1 balun or in my case UNUN does the impedance match.

Any idea why an MMIC was used? I just adds to harmonic and other distortion.

 

I think some more explanation is called for.

I guess you might remember that many moons ago I pasted some pictures of SNA I built from scratch. I was considering posting it to the group but wanted to improve is somewhat and be ready to answer questions regarding the HW/SW.  I could not get around to doing it due to some bit of illness. ( It was all assembly so hard to remember the details)  During this time I decided to learn some embedded C and as an exercise to rewrite the SNA SW in C. I also did not like the slow serial connect to the Graphic LCD ( GLCD!) etc. S0 I decided to use a 3.2 inch GLCD. This one has a 16 bit parallel data interface so the old 32 pin IC would not do and I switched to a more modern C8051F020 from Silicon Labs.

I was looking at the output of the AD9851 and decided that I don't really need the MMIC. I have a few AD9851 boards with the filter built in and decided that a single ended signal take off would do.

I have used a 200 Ohm R on the output of the AD9851 board removed the filter and used a 4:1 Ruthroff UNUN The output is over the top. Enough to do any old testing of networks.

The output level is calculated as follows. ( excluding the attenuation of any built in LP filter. I have removed mine)

The Peak I out is 10mA.  The 200 ohms at the output and the 50 ohms reflected as 200 ohms at the output of the SNA = total 100 Ohms. The 10 mA x 100 ohms gives a peak of 1000 mV and 0.707 V rms output which reduces to .707/2 =353 mV rms at the SNA terminals ( UNUN). This equals +4dBm

Enough for my needs. The out impedance is 50 Ohms. I intend to build a few small external filters for use in different applications. Sweep scan is variable from 480 Hz to 50 MHz. I think the fastest  scan is 300mSec. Slowest is several seconds.

 

I will try upload the pictures and schematic and SW as soon as I am happy with the details. It is written in C except a few fast routines for the GLCD  in Assembly.  I have used no library routines as  all is home brew. and the SW is as efficient as I could make it. This is an 8051 U-controller so some people might not be familiar but it is the best uC  in the world. ( In my view, that is)

I think the real DIY guys should find it interesting.


 73


Azzythehillbilly