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Si5351 minimalist routine

CO6EGM
 

Hello guys... I need a little help from you. I’m working on a old radio restoration... I’m replacing the PLL unit for a Raduino board, but I need a 200KHz signal for the BFO. I was carefully reading the standalone routine, but I can’t understand how to modify it to get frequencies lower than 500 KHz... any ideas???
The firmware that I’m using is CEC v1.21

Gordon Gibby
 

The device can go down into the single-digit kilohertz range. So you’re just going to have to modify the software to get it there. Look at this data  sheet, and then go learn about how it is Programmed. 

That is probably the easiest way, but there is another one also..  Put in a decade counter.   It will divide by 10 for you.   If you need to make it a sine wave at a low pass filter afterwards.  


On Aug 6, 2019, at 21:28, CO6EGM <co6egm@...> wrote:

Hello guys... I need a little help from you. I’m working on a old radio restoration... I’m replacing the PLL unit for a Raduino board, but I need a 200KHz signal for the BFO. I was carefully reading the standalone routine, but I can’t understand how to modify it to get frequencies lower than 500 KHz... any ideas???
The firmware that I’m using is CEC v1.21

Jerry Gaffke
 

I assume the CEC firmware is using the si5351bx routines that I wrote
for the Bitx40 and uBitx as found here.  https://github.com/afarhan/ubitx
In those routines is this comment:

// Most users will never need to generate clocks below 500khz.
// But it is possible to do so by loading a value between 0 and 7 into
// the global variable si5351bx_rdiv, be sure to return it to a value of 0
// before setting some other CLK output pin.  The affected clock will be
// divided down by a power of two defined by  2**si5351_rdiv
// A value of zero gives a divide factor of 1, a value of 7 divides by 128.
// This lightweight method is a reasonable compromise for a seldom used feature.

Here's some example code that will cause clk1 to operate at 200khz:

si5351bx_init();                             // typically happens only once at power up

si5351bx_rdiv = 3;                      // Tell the output rdiv stage to divide by 2**3 = 8
si5351bx_setfreq(1, 1600000);    // Tell clk1 to operate at 1600khz, output will be 1600khz/8 = 200khz
si5351bx_rdiv = 0;                        // Back to normal mode so does not affect updates to ckl0 or clk1

No other calls into the si5351bx routines are needed, that is a complete example.

Note that I'm using the same rdiv variable for all three clocks.
That makes it a bit cumbersome, but then the *Bitx* rigs never need it.

Jerry, KE7ER


On Tue, Aug 6, 2019 at 06:28 PM, CO6EGM wrote:
Hello guys... I need a little help from you. I’m working on a old radio restoration... I’m replacing the PLL unit for a Raduino board, but I need a 200KHz signal for the BFO. I was carefully reading the standalone routine, but I can’t understand how to modify it to get frequencies lower than 500 KHz... any ideas???
The firmware that I’m using is CEC v1.21

Ashhar Farhan
 

i have an even more general routine set derived from Jerry's work here:

- f

On Wed, Aug 7, 2019 at 11:24 AM Jerry Gaffke via Groups.Io <jgaffke=yahoo.com@groups.io> wrote:
I assume the CEC firmware is using the si5351bx routines that I wrote
for the Bitx40 and uBitx as found here.  https://github.com/afarhan/ubitx
In those routines is this comment:

// Most users will never need to generate clocks below 500khz.
// But it is possible to do so by loading a value between 0 and 7 into
// the global variable si5351bx_rdiv, be sure to return it to a value of 0
// before setting some other CLK output pin.  The affected clock will be
// divided down by a power of two defined by  2**si5351_rdiv
// A value of zero gives a divide factor of 1, a value of 7 divides by 128.
// This lightweight method is a reasonable compromise for a seldom used feature.

Here's some example code that will cause clk1 to operate at 200khz:

si5351bx_init();                             // typically happens only once at power up

si5351bx_rdiv = 3;                      // Tell the output rdiv stage to divide by 2**3 = 8
si5351bx_setfreq(1, 1600000);    // Tell clk1 to operate at 1600khz, output will be 1600khz/8 = 200khz
si5351bx_rdiv = 0;                        // Back to normal mode so does not affect updates to ckl0 or clk1

No other calls into the si5351bx routines are needed, that is a complete example.

Note that I'm using the same rdiv variable for all three clocks.
That makes it a bit cumbersome, but then the *Bitx* rigs never need it.

Jerry, KE7ER


On Tue, Aug 6, 2019 at 06:28 PM, CO6EGM wrote:
Hello guys... I need a little help from you. I’m working on a old radio restoration... I’m replacing the PLL unit for a Raduino board, but I need a 200KHz signal for the BFO. I was carefully reading the standalone routine, but I can’t understand how to modify it to get frequencies lower than 500 KHz... any ideas???
The firmware that I’m using is CEC v1.21

CO6EGM
 

Thanks Jerry for the example... I was studying your routine, but on the CEC firmware it was rdiv=0 at all times... I’m working on a new synthesizer for my RFT SEG15D, but also I’m wanna help a lot of friends on Cuba that have the same rig out of service due to PLL issues... over there is so difficult to fix it. I know a $15 part is considered a luxury part on my country, but it’s better than get a lot of headaches with the original PLL . 
I also need to say thanks to Ashar Farhan for the Raduino and also for the bitx family... Very simple and effective circuits..,

Jerry Gaffke
 

This is the first time I have heard of anybody using the si5351bx routines
with a non-zero rdiv.  Good to hear that you have found a good home for it.
Give my regards to your friends in Cuba.

Jerry


On Wed, Aug 7, 2019 at 07:06 AM, CO6EGM wrote:
Thanks Jerry for the example... I was studying your routine, but on the CEC firmware it was rdiv=0 at all times... I’m working on a new synthesizer for my RFT SEG15D, but also I’m wanna help a lot of friends on Cuba that have the same rig out of service due to PLL issues... over there is so difficult to fix it. I know a $15 part is considered a luxury part on my country, but it’s better than get a lot of headaches with the original PLL . 
I also need to say thanks to Ashar Farhan for the Raduino and also for the bitx family... Very simple and effective circuits..,

Robert McClements
 

Jerry, thank you for the explanation which I also stumbled accross in the CEC sketch comments.
Works well, starting with a divisor of 4 to generate a fixed output of 200kHz
then rdiv back to 0 to give normal frequency generation above 500kHz.

73, Bob GM4CID