Topics

SI5351 quadrature VFO

Miguel Angelo Bartie
 

Hello Guys

In my home page the new VFO in quadrature using SI5351 and Arduino nano.
from 4.76 to 220MHz ...direct 90 degrees phase shifting. TRX #183


http://py2ohh.w2c.com.br/

73 de py2ohh miguel

Miguel Angelo Bartie
 

I forgot to add the sketch ...now is OK

73 from py2ohh miguel

Ashhar Farhan
 

Miguel,
Your work is always inspiring, thanks for this. It is a keeper. 
73, f

On Wed, 13 Jun 2018, 16:29 Miguel Angelo Bartie via Groups.Io, <py2ohh=yahoo.com.br@groups.io> wrote:
Hello Guys

In my home page the new VFO in quadrature using SI5351 and Arduino nano.
from 4.76 to 220MHz ...direct 90 degrees phase shifting. TRX #183


http://py2ohh.w2c.com.br/

73 de py2ohh miguel

Ian Lee
 

Miguel

It's awesome. I'm going to experiment this weekend.
I thought you could do it. cool.

Ian

2018-06-13 20:54 GMT+09:00 Miguel Angelo Bartie via Groups.Io <py2ohh@...>:

I forgot to add the sketch ...now is OK

73 from py2ohh miguel



--
Best 73
KD8CEC / Ph.D ian lee
kd8cec@...
www.hamskey.com (my blog)

Hans Summers
 

Hi Miguel, all

I saw in the English Google translation of you web page that you had questions about how to get down to 3.2MHz with the Si5351A configured in Quadrature LO. The answer is that you must abandon the 600-900MHz limit on the Si5351A internal VCO. The lower limit at which you can configure the VCO is something like 400MHz (I forget the exact number), and 400MHz / 126 = 3.2MHz. 

Three requirements for a silky smooth, click-free, quadrature LO that tracks at precisely 90-degrees across the whole band as seen in the QCX 5W CW transceiver http://qrp-labs.com/qcx are:

1) Set the MultiSynth division stage to an even integer between 4 and 126. Set the phase offset register to the same number. And leave them, don't alter again, unless you make a huge frequency change (e.g. 10MHz) and find you need to change the MultiSynth division again. Configure the first stage, the VCO PLL, with a fractional divider. Note that this is the OPPOSITE way around to the NT7S library which uses a fixed integer up-multiplication to the VCO, then a fractional MultiSynth division in the second stage. Quadrature LO cannot be obtained unless you fix the MultiSynth divider stage to an integer, and vary the PLL (VCO) for the actual frequency changes. In any case, the SiLabs documentation recommends even integer divider for the MultiSynth stage for lowest output jitter (phase noise). Therefore it's a good idea to do it this way, anyway - even if you aren't looking for a quadrature LO. 

2) Do NOT do a PLL Reset (by setting the PLL Reset register bits in the Si5351A) at every frequency change! Only do a Reset when you change the MultiSynth Divider. Here, the reset is absolutely required in order to set up the initial phase relationship correctly between the two outputs. But you do NOT need a PLL Reset subsequently when you change the frequency, even when you change the frequency by a substantial amount. Doing a PLL Reset WILL create loud audible clicks. 

3) Do NOT be tempted to try to switch off Si5351A outputs during frequency changes. It also generates clicks (albeit lesser ones). It is a bad solution to the problem of clicks, because it does not tackle the real problem (unnecessary PLL Reset commands), it only masks the problem slightly. As long as you heed my advice in 2) above you will never need to temporarily switch off Si5351A outputs. 

These lessons were all learned the HARD way over the last three years, during QRP Labs products firmware development (and evolution). Unfortunately there was no easy way, due to the poor SiLabs documentation. Now the easier way is to learn from others' mistakes :-)   (a.k.a. MINE). All of this is described in more detail in my Dayton FDIM 2018 seminar accompanying article, the PDF is available here http://www.qrp-labs.com/dayton2018.html

73 Hans G0UPL

Jerry Gaffke
 

Hans,

By all reports, the QCX is a great product at a great price.
And we appreciate the care you have taken to document this and your other products.

I'm curious, have you measured the increase in jitter when going to a fractional output msynth on the si5351?
Not clear to me whether or not this is a significant consideration for the uBitx.

While AN619 does recommend holding it in integer mode for minimum jitter, 
the si5338 docs (a sister part that is better documented) suggest the increase in jitter is well under a factor of two.
Also, I have found that ClockBuilderPro from SiLabs leaves the output msynth in fractional modes, but does
an exhaustive search for an a+b/c with small values for b and c.

Another issue, the uBitx uses all three clocks out of the si5351, and with only two PLL's available in the si5351
it's at least bothersome if not impractical to keep all three output msynth's in integer mode.
I agree that you must be in integer mode to use the phase shift feature to get quadrature clocks, but that
is not a requirement on the uBitx. 
(Very nice to know that the vco can work well beyond the 600-900 mhz spec, thanks!)

We could, however, use PLLA on clk2 as you suggest, with an integer output msynth.
Choose the PLLB frequency based on the required (mostly fixed) frequency of clk1 into the second mixer,
so this could also have an integer output msynth.
The bfo on clk0 is only at 12mhz, so could use  PLLB) along with a fractional output msynth.   
At 12mhz versus a maximum vfo frequency of 30+45=75mhz, the jitter of this bfo will be far less than
the vfo in spite of the fractional output msynth.

But this would complicate the si5351bx routines considerably, also increase the amount of flash used.
Unless jitter is known to be an issue on the uBitx, I am inclined not to bother.
A better fix might be to build a Raduino that uses the lower jitter (and lower crosstalk) si5338,
especially for those wishing to extend the uBitx for use as a VHF rig.

Jerry, KE7ER


On Thu, Jun 14, 2018 at 07:29 am, Hans Summers wrote:
Hi Miguel, all
 
I saw in the English Google translation of you web page that you had questions about how to get down to 3.2MHz with the Si5351A configured in Quadrature LO. The answer is that you must abandon the 600-900MHz limit on the Si5351A internal VCO. The lower limit at which you can configure the VCO is something like 400MHz (I forget the exact number), and 400MHz / 126 = 3.2MHz. 
 
Three requirements for a silky smooth, click-free, quadrature LO that tracks at precisely 90-degrees across the whole band as seen in the QCX 5W CW transceiver http://qrp-labs.com/qcx are:
 
1) Set the MultiSynth division stage to an even integer between 4 and 126. Set the phase offset register to the same number. And leave them, don't alter again, unless you make a huge frequency change (e.g. 10MHz) and find you need to change the MultiSynth division again. Configure the first stage, the VCO PLL, with a fractional divider. Note that this is the OPPOSITE way around to the NT7S library which uses a fixed integer up-multiplication to the VCO, then a fractional MultiSynth division in the second stage. Quadrature LO cannot be obtained unless you fix the MultiSynth divider stage to an integer, and vary the PLL (VCO) for the actual frequency changes. In any case, the SiLabs documentation recommends even integer divider for the MultiSynth stage for lowest output jitter (phase noise). Therefore it's a good idea to do it this way, anyway - even if you aren't looking for a quadrature LO. 
 
2) Do NOT do a PLL Reset (by setting the PLL Reset register bits in the Si5351A) at every frequency change! Only do a Reset when you change the MultiSynth Divider. Here, the reset is absolutely required in order to set up the initial phase relationship correctly between the two outputs. But you do NOT need a PLL Reset subsequently when you change the frequency, even when you change the frequency by a substantial amount. Doing a PLL Reset WILL create loud audible clicks. 
 
3) Do NOT be tempted to try to switch off Si5351A outputs during frequency changes. It also generates clicks (albeit lesser ones). It is a bad solution to the problem of clicks, because it does not tackle the real problem (unnecessary PLL Reset commands), it only masks the problem slightly. As long as you heed my advice in 2) above you will never need to temporarily switch off Si5351A outputs. 
 
These lessons were all learned the HARD way over the last three years, during QRP Labs products firmware development (and evolution). Unfortunately there was no easy way, due to the poor SiLabs documentation. Now the easier way is to learn from others' mistakes :-)   (a.k.a. MINE). All of this is described in more detail in my Dayton FDIM 2018 seminar accompanying article, the PDF is available here http://www.qrp-labs.com/dayton2018.html
 
73 Hans G0UPL

freefuel@...
 

Jerry, that Si5338 while it has four outputs it only has a single PLL, it would seem that only a single PLL to work with would compound the jitter/phase noise problem if there really is one in the uBITX. 

-Justin N2TOH 

freefuel@...
 

Miguel, if you could get that output up around 225MHz that would be great for those of us in the United States. 

-Justin N2TOH 

Jerry Gaffke
 

Yes, the si5338 has one pll.
But with that single pll, the output msynths are done accurately enough that jitter is better than can be done on the si5351
using integer output msynths.

Also, you do realize that the uBitx uses only one of the two PLL's inside the si5351?
The si53351 has two pll's but the second pll is not used.
The uBitx requires three clock.
As described in my previous email.

Jerry


On Thu, Jun 14, 2018 at 03:12 pm, <freefuel@...> wrote:
Jerry, that Si5338 while it has four outputs it only has a single PLL, it would seem that only a single PLL to work with would compound the jitter/phase noise problem if there really is one in the uBITX. 

Hans Summers
 




Hi Jerry 

> I'm curious, have you measured the increase in jitter when going to a 
> fractional output msynth on the si5351?
> Not clear to me whether or not this is a significant consideration for the uBitx.

No, I have not measured it. In my opinion it is not likely to be a problem. As you mention, SiLabs do various tricks in the silicon that reduce jitter. I agree that the difference between the two modes may be a factor of 2 or less. Both of them are surely fine and better than the LC VFOs everyone was happy with for a century. Elecraft use the Si5351A as the VFO in the KX2, I'd like to hope that also confirms it can't be bad :-)

But still I prefer the use of the even integer divisor, and I have always used it this way. And it allows the quadrature mode if that is desired. 

> Another issue, the uBitx uses all three clocks out of the si5351, and with only 
> two PLL's available in the si5351 it's at least bothersome if not impractical to keep all three 
> output msynth's in integer mode. I agree that you must be in integer mode to use the phase 
> shift feature to get quadrature clocks, but that is not a requirement on the uBitx. 

Yes that's a very good point that I had forgotten. Not just bothersome or impractical; but in the general case impossible... there are three outputs (with three MultiSynth dividers) but only two PLLs. So if you want to use three outputs all on different frequencies, then the third MUST use fractional MultiSynth division. Unless you are lucky enough that your third frequency is somehow related to one of the others, such that it can use an integer division too. 

I do use the fractional division mode in my ProgRock kit http://qrp-labs.com/progrock which supports three independent frequency outputs. So I use even integer on two outputs and MultiSynth fractional division on the third. 

One other comment... 

Use of floating point arithmetic greatly increases the code size. And execution time - but generally I have found the execution time is not usually a constraint, neither is RAM or EEPROM... the biggest constraint I run into is the Flash program memory size. 64-bit arithmetic increases the code size even worse than floating point. Accordingly I use only 32-bit unsigned integer arithmetic in my Si5351A configuration routines in my firmware. It is possible to do all the calculations in 32-bit arithmetic without losing any precision (Floating point loses precision, 64-bit increases the code size too much). The result is compact code and accurate. 

73 Hans G0UPL

Jerry Gaffke
 

Hans,

Code for the uBitx has been using my si5351bx routines since day one. 
Allards Bitx40 code also uses these routines starting summer of 2017.
The uBitx routines are also 32 bit fixed point math. 
Precision was within about 10ppb as I recall.
So the uBitx tuning is correct within about 30e6/10e9 =  0.3 Hz when operating at 30mhz, is proportionally better as you go down in frequency,
the 25mhz reference oscillator will vary by far more than that with slight variations in temperature.
Of course, the calibration must be done correctly per post 35235 to approach this kind of accuracy.
Judging from all the posts to the forum about having to take multiple runs to calibrate vfo and bfo and clk1, 
most uBitx software releases out there have not yet gotten this right. 

Primary execution time constraint is shoveling all those i2c bits out to the si5351 at 100khz,
could be bumped up to 400khz if that's of concern.

The uBitx shuts down clk0 and clk1 when transmitting CW, this avoids any possibility of 
those mixer products getting out to the antenna.  A slight speed-up of maybe 10 milliseconds could be had
by only touching the clock-enable bits in si5351 register 3 to turn these off and on rather than 
loading all those msynth registers each time.  Doesn't really matter unless attempting 
full break-in for high speed CW with solid state TR switching.

Jerry, KE7ER



On Thu, Jun 14, 2018 at 10:27 pm, Hans Summers wrote:
Use of floating point arithmetic greatly increases the code size. And execution time - but generally I have found the execution time is not usually a constraint, neither is RAM or EEPROM... the biggest constraint I run into is the Flash program memory size. 64-bit arithmetic increases the code size even worse than floating point. Accordingly I use only 32-bit unsigned integer arithmetic in my Si5351A configuration routines in my firmware. It is possible to do all the calculations in 32-bit arithmetic without losing any precision (Floating point loses precision, 64-bit increases the code size too much). The result is compact code and accurate. 
 

Ashhar Farhan
 

Are you sure these work upto 290 mhz? 

Jerry Gaffke
 

As I recall, Hans reported that the samples he tested did work up to 290mhz,
above which they definitely failed.

If you want to be sure, then should follow the datasheet spec.    
    https://www.silabs.com/documents/public/data-sheets/Si5351-B.pdf

Or go to a different part
    https://www.silabs.com/documents/public/data-sheets/Si5338.pdf

Datasheet says the si5351 has a vco max of 900 mhz and output msynth min of 4,
so that suggests it could do 900/4 = 225mhz. 
Datasheet also says a max output clock of 200 mhz, I'd guess beyond that
they can't guarantee proper CMOS logic levels from the driver.

To hit 290 mhz, the vco must be operating at 290*4 = 1160 mhz.
Jitter might be getting bad, as the vco loop filter is not designed for this.
Heat could also cause trouble. 

Jerry, KE7ER 


On Fri, Jun 15, 2018 at 08:31 am, Ashhar Farhan wrote:
Are you sure these work upto 290 mhz? 

Hans Summers
 

Hi Farhan

> Are you sure these work upto 290 mhz? 

According to the datasheet specification the top frequency is 200MHz. 

However if you ignore this and just configure it for higher and higher frequencies, in my test it really did seem to work fine up until 290MHz. After that the output just gives up. Other QRP Labs kit owners also verified similar maximum frequency around 300MHz.

Of course I have no idea what performance specification may be violated, or no longer guaranteed under all specified conditions, at 290MHz. The wisdom of using the chip up so far outside its specification is debatable, particularly in anything other than a one-off homebrew project. 

73 Hans G0UPL 

Ashhar Farhan
 

Hans,
My question wasn't clear enough. I was asking if the library worked to 290 MHz. Above 150 Mhz, integeral divider is needed. There was some overflow with jerry's code. 
That apart, i see some sidebands about -40dbc on both sides of the signal, a few hundred kilohertz on either sides. They appear only on specific frequencies. 
I am really interested in using the Si5351 on 435 MHz. I pushed a 150 Mhz signal out of the Si5351 into a 450 Mhz band pass filter (doubly tuned, promixally coupled). It gave about -4dbm out of the band pass filter, A MMIC raises it to the obligatory +7dbm. 

- f

On Sat, Jun 16, 2018 at 12:00 AM, Hans Summers <hans.summers@...> wrote:
Hi Farhan

> Are you sure these work upto 290 mhz? 

According to the datasheet specification the top frequency is 200MHz. 

However if you ignore this and just configure it for higher and higher frequencies, in my test it really did seem to work fine up until 290MHz. After that the output just gives up. Other QRP Labs kit owners also verified similar maximum frequency around 300MHz.

Of course I have no idea what performance specification may be violated, or no longer guaranteed under all specified conditions, at 290MHz. The wisdom of using the chip up so far outside its specification is debatable, particularly in anything other than a one-off homebrew project. 

73 Hans G0UPL 


Hans Summers
 

Hi Farhan

> My question wasn't clear enough. I was asking if 
> the library worked to 290 MHz. 

Ah I see... have no idea about the library... my various firmware implementations do all work up to 290MHz. The integer /4 limitation anyway results naturally out of my code since I'm using even integer MultiSynth anyway (except for the one exception where I need three independent general purpose outputs).

73 Hans G0UPL 

Ashhar Farhan
 

Which library do you recommend with the synth kit?

- f

On Sat, Jun 16, 2018 at 1:04 AM, Hans Summers <hans.summers@...> wrote:
Hi Farhan

> My question wasn't clear enough. I was asking if 
> the library worked to 290 MHz. 

Ah I see... have no idea about the library... my various firmware implementations do all work up to 290MHz. The integer /4 limitation anyway results naturally out of my code since I'm using even integer MultiSynth anyway (except for the one exception where I need three independent general purpose outputs).

73 Hans G0UPL 


Jerry Gaffke
 

Jerry's code "overflows" at anything above 875/8 = 109 mhz because no attempt was made
to support integer mode output msynth values, that should be clear enough from the comments.
Actually what it does is shut down that output clock to make it clear that you have screwed up. 

Any output msynth of less than 8.0 must be an integer of either 6 or 4.
Greater than 8.0, the output msynth can take on fractional values.
So with the vco at the max of 900 mhz (I was using 875mhz), the absolute max output 
frequency for fractional output msynths within the datasheet spec is 900/8 = 112.5mhz.
Not 150 mhz.

The 150 mhz limitation of many si5351 libraries comes from the fact that 6*150=900 mhz,
so that's the limit of an output msynth integer divide of 6.
An output msynth divide of 4 requires some special case code, though it is fairly trivial.

To add support to the si5351bx routines for integer output msynth values and fractional vco msynth values
is easy enough, but doubles the amount of flash required.  Also complicates the user interface.
No point in doing any of that when targeting the uBitx.

Phase noise from the vco will be proportional to the output frequency. 
At some point I'd expect trouble there, especially if tripling the si5351 output. 

At what frequencies do you see these sidebands?
Is this with the si5351bx routines?
Or with integer output msynth values using some other library to generate 112.5mhz and greater clocks?

At some point, I think this is best moved to an si5338.
Or an si549 if you really want to get crazy.  1500mhz max.

Jerry, KE7ER



On Fri, Jun 15, 2018 at 11:58 am, Ashhar Farhan wrote:

Hans,
My question wasn't clear enough. I was asking if the library worked to 290 MHz. Above 150 Mhz, integeral divider is needed. There was some overflow with jerry's code. 
That apart, i see some sidebands about -40dbc on both sides of the signal, a few hundred kilohertz on either sides. They appear only on specific frequencies. 
I am really interested in using the Si5351 on 435 MHz. I pushed a 150 Mhz signal out of the Si5351 into a 450 Mhz band pass filter (doubly tuned, promixally coupled). It gave about -4dbm out of the band pass filter, A MMIC raises it to the obligatory +7dbm. 
 
- f

gaurav srivastava
 

Hello Miguel,
I have seen the video on you tube and you have done a remarkable job.
I am unable to find the sketch on the above link
Can you please share the link to me on my email VU3RQX@...

73

VU3RQX

Miguel Angelo Bartie
 

Hello Guys

I changed the NT7S library - only one line - the minimum PLL frequency from 600MHz to 400MHz...now it is ok from 3.2 to 110MHz ..

http://py2ohh.w2c.com.br/trx/si5351quadra/si5351quadra.html

in the link you can see the sketch and a link to the new library.

73 from py2ohh miguel

.