Re: i2c encoders in matrix with I/O #ubitx

Gary Anderson

On the hardware side, the interrupt pin INT, is an open drain asserted low signal (maybe better described as INT_B).  This node can be wired OR'd. ( 'daisy-chained' as John described)
The software will need to scan/poll each device to determine which module(s) asserted an interrupt, and service it  or them appropriately.


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