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I think that's a very interesting idea - a couple of thoughts that might be useful (or not) - you may already be well aware of these:
1) 120MHz signaling can be hard to wire, especially in wide parallel buses - this may be difficult to wire without signal integrity errors, unless you're laying out a board for the task. 12-bit sampling just increases the number of lines you're trying to keep synchronized. Modern FPGAs shouldn't have an issue running I/O at 120MHz, but you will probably need terminated signal paths and matched cable lengths to ensure data transport
2) Your dynamic range will be limited by the 10- or 12-bit sample depth; oversampling can help, but it might be more effective to get a 14- or 16-bit ADC at a slower clock rate than to oversample at a lower depth. It's been a while since I've looked at the math; I'm sure several people on the list are smarter than me about this! If you incorporate AGC, this should help considerably (but close-in signals will still affect your dynamic range, obviously). I might even consider sub-sampling, although I don't know if you can get ADCs (significantly better than 16-bit, for reasonable cost) that would support 12MHz sub-sampling...
Very, very interesting - I've been thinking about building just such a configuration (at least single-conversion, and then sampling at an HF IF with a fast ADC) for a while, but I'm not really a hardware guy - and I would feel compelled to lay out the ADC and FPGA portion, at minimum, and sounds tedious. I've seen high-speed FPGA designs, and I know that I'm not competent to lay them out :-)
Anyway, good luck - I'd love to hear about the project, if you proceed!
On Thu, Jan 17, 2019 at 10:11 PM Tom, wb6b <wb6b@...> wrote: