Re: Wild and crazy uBITX, Arduino FPGA idea. #arduino #ubitx #sdr #fpga


Joshua Blanton
 

Hello Tom,

I think that's a very interesting idea - a couple of thoughts that might be useful (or not) - you may already be well aware of these:

1) 120MHz signaling can be hard to wire, especially in wide parallel buses - this may be difficult to wire without signal integrity errors, unless you're laying out a board for the task.  12-bit sampling just increases the number of lines you're trying to keep synchronized.  Modern FPGAs shouldn't have an issue running I/O at 120MHz, but you will probably need terminated signal paths and matched cable lengths to ensure data transport

2) Your dynamic range will be limited by the 10- or 12-bit sample depth; oversampling can help, but it might be more effective to get a 14- or 16-bit ADC at a slower clock rate than to oversample at a lower depth.  It's been a while since I've looked at the math; I'm sure several people on the list are smarter than me about this!  If you incorporate AGC, this should help considerably (but close-in signals will still affect your dynamic range, obviously).  I might even consider sub-sampling, although I don't know if you can get ADCs (significantly better than 16-bit, for reasonable cost) that would support 12MHz sub-sampling...

Very, very interesting - I've been thinking about building just such a configuration (at least single-conversion, and then sampling at an HF IF with a fast ADC) for a while, but I'm not really a hardware guy - and I would feel compelled to lay out the ADC and FPGA portion, at minimum, and sounds tedious.  I've seen high-speed FPGA designs, and I know that I'm not competent to lay them out :-)

Anyway, good luck - I'd love to hear about the project, if you proceed!

Josh, KB8NYP

On Thu, Jan 17, 2019 at 10:11 PM Tom, wb6b <wb6b@...> wrote:

Hi,

 

I just received a Arduino MKR Vidor board. It is a higher powered Arduino with a medium sized FPGA included on the board. 

 

My thought was to add a fairly fast (around 120Mhz to allow oversampling) 10 or 12 bit DAC to supply the transmit signal directly to the low pass filter at Test Point 1. And use a 50Mhz 12 bit ADC (again to allow oversampling) for receive picking up the signal at test point 17. 

 

For receive this should be better than trying to push the ADC close to the antenna, as the digital receiver will then have a fairly cleaned up signal to work with and the signal frequency (12Mhz) is fairly moderate. In fact, if the frequency could be mixed down even lower, it might be possible to use fairly low speed ADCs.

 

Another advantage of the band pass filtering ahead of the ADC for receive is there should be no need for quadrature (I/Q) mixers, and dual ADCs, as the digital processing will not need to determine which signal frequencies are above and below the center frequency. (Internally, for SSB demodulation, depending on method, there could be I/Q processing. But that can all be handled in the FPGA). 

 

So the uBITX could be a really good starting point for the RF parts of a FPGA SDR transceiver. It's possible the specs for the ADC and DAC chips could be toned down a bit and reduce the costs further. 

 

Here are a couple of possible designs that could be used as a starting point.

 

http://k6jca.blogspot.com/2017/02/an-fpga-sdr-hf-transceiver-part-1.html

https://www.tapr.org/pdf/DCC2010-FPGA-BasedTransceiver-KD6OZH.pdf

Tom, wb6b


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