Re: uBitx Unfiltered

Jerry Gaffke
 

Here are the changes to file ubitx_si5351bx.ino of Farhan's stock code  that are needed to hit 115mhz.
With this change, the three available clocks can be set to any frequency between 514.5khz and 115.5mhz.
Not tried, but should work.  Must recalibrate after making the change:
 
< #define SI5351BX_MSA  35                // VCOA is at 25mhz*35 = 875mhz
> #define SI5351BX_MSA  37                // VCOA is at 25mhz*37 = 925mhz
 
< if ((fout < 500000) || (fout > 109000000))    // If clock freq out of range
> if ((fout < 514500) || (fout > 115500000))    // Range of 25mhz*37/1800 to 25mhz*37/8, minus 1000ppm calibration margin:


The maximum recommended VCO frequency in the si5351 datasheet is 900mhz, we're operating it at 925mhz.
Hans has found that it seems to work up to frequencies of around 1168mhz, though I suspect phase noise 
becomes an issue if you press it too far.

The min and max available frequencies of 514.5khz and 115.5mhz are determined primarily by the si5351's
fractional output divider range of 1800.0 to 8.0.  The si5351 is also capable of integer output divide values
of 4 and 6, but the code does not support this.   

When calculating those output divider values, we use the actual vco frequency as determined by
the calibration procedure, not the nominal vco frequency of 25mhz*37=925.000mhz.
The suggested min and max values in the code above assume the 25mhz reference oscillator might be off by as
much as 1000ppm, due largely to a too-small crystal loading capacitance for the crystal used.

The code also assumes that the vco operates at integer multiple of 25mhz, so the next step up 
from 900mhz is 925mhz.  Arbitrary values such as 920mhz are possible using a fractional vco feedback divider,
but the code does not currently support this.

With significant modifications to the code, we could allow one of the three clocks to hit any frequency 
up to 200mhz (according to the datasheet, Hans found it more or less worked up to 1168/4=292mhz).
This would be accomplished by using the second si5351 vco in fractional feedback mode to 
hit any desired frequency between the datasheet limits of 600mhz and 900mhz, then use an
arbitrary output divide value (use an even integer to get minimum phase noise) to take the vco
down to the desired operating frequency.  A major rewrite of the code, would require double the
flash space.  The other two clocks would still use the original si5351bx code, dividing the
first vco (kept at a fixed frequency of perhaps 875mhz) down by the fractional output dividers.

Jerry, KE7ER



On Sat, Sep 1, 2018 at 06:48 PM, Jerry Gaffke wrote:
Easy enough to get the si5351 to hit 115mhz.

One possibility, just run the vco at 920mhz instead of 900 mhz,
a wee bit out of spec but will work fine.
No changes to the code other than some constants in the si5351bx code,
must the recalibrate of course.

Alternately, use the second PLL inside the si5351 to 85 to 115mhz out to clk2,
si5351 output divider for clk2 fixed at 6.
Might be possible to do this using the etherkit si5351 library,
or a major hack to the si5351bx routines.
The G0UPL library might also do it, though I believe it is restricted to two outputs.

Jerry, KE7ER
toggle quoted message. . .

 


On Sat, Sep 1, 2018 at 03:59 PM, ajparent1/KB1GMX wrote:
Also the HFO (osc-3) has to go from 85mhz to 115 mhz and that meas you
exceed the SI5351 code by 6mhz.

// the output msynth dividers are used to generate 3 independent clocks
// with 1hz resolution to any frequency between 4khz and 109mhz.

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