Re: uBitx Unfiltered

Jerry Gaffke
 

Easy enough to get the si5351 to hit 115mhz.

One possibility, just run the vco at 920mhz instead of 900 mhz,
a wee bit out of spec but will work fine.
No changes to the code other than some constants in the si5351bx code,
must the recalibrate of course.

Alternately, use the second PLL inside the si5351 to 85 to 115mhz out to clk2,
si5351 output divider for clk2 fixed at 6.
Might be possible to do this using the etherkit si5351 library,
or a major hack to the si5351bx routines.
The G0UPL library might also do it, though I believe it is restricted to two outputs.

Jerry, KE7ER


On Sat, Sep 1, 2018 at 03:59 PM, ajparent1/KB1GMX wrote:
Also the HFO (osc-3) has to go from 85mhz to 115 mhz and that meas you
exceed the SI5351 code by 6mhz.

// the output msynth dividers are used to generate 3 independent clocks
// with 1hz resolution to any frequency between 4khz and 109mhz.

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