As far as I know, and have used, the physical layer (e.g. hardware) is defined as an open drain / open collector. I haven't seen the Ap note. If you have a link you could share, I would like to review.
For bit banging with a standard digital I/O port. You set the port as an input, set the drive state to 0. You bit bang between input and output states.
For the case we have here, between a 3.3V and 5V device, the pull-up to 3.3V Si5351 meets/ exceeds the VIH of the 5V Nano, so all is good.
However, if you need to interface between say a 1.2V or 1.8V to a 5V I/O you would need to level shift...... I see how this Ap note could be going now.
I will admit, that I read you post under a fog of too many folks are destroying Nanos. I'd rather have a discussion then a fellow ham wondering why something went wrong when it worked fine yesterday.