Re: SI5351 quadrature VFO

Jerry Gaffke
 

Hans,

By all reports, the QCX is a great product at a great price.
And we appreciate the care you have taken to document this and your other products.

I'm curious, have you measured the increase in jitter when going to a fractional output msynth on the si5351?
Not clear to me whether or not this is a significant consideration for the uBitx.

While AN619 does recommend holding it in integer mode for minimum jitter, 
the si5338 docs (a sister part that is better documented) suggest the increase in jitter is well under a factor of two.
Also, I have found that ClockBuilderPro from SiLabs leaves the output msynth in fractional modes, but does
an exhaustive search for an a+b/c with small values for b and c.

Another issue, the uBitx uses all three clocks out of the si5351, and with only two PLL's available in the si5351
it's at least bothersome if not impractical to keep all three output msynth's in integer mode.
I agree that you must be in integer mode to use the phase shift feature to get quadrature clocks, but that
is not a requirement on the uBitx. 
(Very nice to know that the vco can work well beyond the 600-900 mhz spec, thanks!)

We could, however, use PLLA on clk2 as you suggest, with an integer output msynth.
Choose the PLLB frequency based on the required (mostly fixed) frequency of clk1 into the second mixer,
so this could also have an integer output msynth.
The bfo on clk0 is only at 12mhz, so could use  PLLB) along with a fractional output msynth.   
At 12mhz versus a maximum vfo frequency of 30+45=75mhz, the jitter of this bfo will be far less than
the vfo in spite of the fractional output msynth.

But this would complicate the si5351bx routines considerably, also increase the amount of flash used.
Unless jitter is known to be an issue on the uBitx, I am inclined not to bother.
A better fix might be to build a Raduino that uses the lower jitter (and lower crosstalk) si5338,
especially for those wishing to extend the uBitx for use as a VHF rig.

Jerry, KE7ER


On Thu, Jun 14, 2018 at 07:29 am, Hans Summers wrote:
Hi Miguel, all
 
I saw in the English Google translation of you web page that you had questions about how to get down to 3.2MHz with the Si5351A configured in Quadrature LO. The answer is that you must abandon the 600-900MHz limit on the Si5351A internal VCO. The lower limit at which you can configure the VCO is something like 400MHz (I forget the exact number), and 400MHz / 126 = 3.2MHz. 
 
Three requirements for a silky smooth, click-free, quadrature LO that tracks at precisely 90-degrees across the whole band as seen in the QCX 5W CW transceiver http://qrp-labs.com/qcx are:
 
1) Set the MultiSynth division stage to an even integer between 4 and 126. Set the phase offset register to the same number. And leave them, don't alter again, unless you make a huge frequency change (e.g. 10MHz) and find you need to change the MultiSynth division again. Configure the first stage, the VCO PLL, with a fractional divider. Note that this is the OPPOSITE way around to the NT7S library which uses a fixed integer up-multiplication to the VCO, then a fractional MultiSynth division in the second stage. Quadrature LO cannot be obtained unless you fix the MultiSynth divider stage to an integer, and vary the PLL (VCO) for the actual frequency changes. In any case, the SiLabs documentation recommends even integer divider for the MultiSynth stage for lowest output jitter (phase noise). Therefore it's a good idea to do it this way, anyway - even if you aren't looking for a quadrature LO. 
 
2) Do NOT do a PLL Reset (by setting the PLL Reset register bits in the Si5351A) at every frequency change! Only do a Reset when you change the MultiSynth Divider. Here, the reset is absolutely required in order to set up the initial phase relationship correctly between the two outputs. But you do NOT need a PLL Reset subsequently when you change the frequency, even when you change the frequency by a substantial amount. Doing a PLL Reset WILL create loud audible clicks. 
 
3) Do NOT be tempted to try to switch off Si5351A outputs during frequency changes. It also generates clicks (albeit lesser ones). It is a bad solution to the problem of clicks, because it does not tackle the real problem (unnecessary PLL Reset commands), it only masks the problem slightly. As long as you heed my advice in 2) above you will never need to temporarily switch off Si5351A outputs. 
 
These lessons were all learned the HARD way over the last three years, during QRP Labs products firmware development (and evolution). Unfortunately there was no easy way, due to the poor SiLabs documentation. Now the easier way is to learn from others' mistakes :-)   (a.k.a. MINE). All of this is described in more detail in my Dayton FDIM 2018 seminar accompanying article, the PDF is available here http://www.qrp-labs.com/dayton2018.html
 
73 Hans G0UPL

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