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BTW I’m using the MCP3202… SPI and dual channel with Sample and Hold…



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From: [] On Behalf Of Jerry Gaffke via Groups.Io
Sent: Sunday, May 6, 2018 9:39 PM
Subject: Re: [BITX20] SWR


Here's the datasheet:
Pages 20-23 are of interest.
Looks to me like it is on the order of 10 bytes transferred via the i2c bus for each ADC read,
since we have to switch channels between reads to choose forward vs reflected power.
At 100 khz, that's 10us * 10 * 8bits/byte = 800 us.
That's an order of magnitude slower than reading the Nano's ADC using a an analogRead() call, around 100us.

It is possible to speed the i2c bus up from 100 khz to 400 khz,
But we can speed up the Nano ADC reads by a factor of 5, fiddling with the ADC clock prescaler.

So using the Nano's ADC is much faster than using this i2c ADC chip
Now if you found a good SPI ADC chip, that might be a different story.



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