Re: SI5351 simultaneous clock changes #ubitx-help

John <passionfruit88@...>

Thanks Jerry, great ideas. 

I will try the delayed single write and report what happens.

My objective is to have a software ALC or power limiter for SSB (and mainly for digital modes) where I can control the output power. Since I measure the forward power continuously my thinking is to use the slope of the first IF filter like I do with the software AGC.

In Rx there is a very slight "pop" when the increase of both clock 1 and 2 occurs (see Ian's Youtube video) and I suspect this is related to the time difference between the changes.

The effect is barely noticeable, but in TX I may for a millisecond or so transmit on a frequency 4 or 6 khz away from the current one. Since I don't think that is good practice I am researching how to avoid it.

Worse case scenario I will disable the clocks, change frequency then re-enable them as you mentioned.

Hope that makes sense.

Thanks and 73, John (VK2ETA)

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