It appears ham rtty speed fsk is quite feasible on SI5351.
especially the paragraph that says
"Additional comment which solved the problem: Kicking up the
Wire library speed from 100kHz to 400kHz with
Wire.setClock(400000L);and using a bulk transfer to shove out a
pre-calculated array of 8 bytes that is MultiSynth0's new
divisor (instead of sending
register1-byte1-register2-byte2-etc). The Si5351 supports bulk
transfer with automatic address increments, so a whole new setup
for MS0 was a total of 9 sent bytes. (Initial address plus the
eight bytes of divisor+number+denominator.) This took the
minimum pulse down to about 0.4ms, well below the 1ms I
makes me believe it would be viable, maybe even at I2C bus speed
of 100 kHz.